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TSC80251
TSC 80251 Programmer's Guide
REV C - 1999
Rev. C - May 7, 1999
TSC80251
TEMIC Semiconductors reserves the right to make changes in the specifications contained in this document in order to improve design or performance and to supply the best possible products. TEMIC also assumes no responsibility for the use of any circuits described herein, conveys no license under any patents or other rights, and makes no representations that the circuits are free from patent infringement. Applications for any integrated circuits contained in this publication are for illustration purposes only and TEMIC makes no representation or warranty that such applications will be suitable for the use specified without further testing or modification. Reproduction of any portion hereof without the prior written consent of TEMIC is prohibited.
On line information
World Wide Web: http://www.temic-semi.com
Factory Technical Support
Email: c251@temic-semi.com
Publisher
MHS S.A. La Chantrerie - Route de Gachet, BP 70602 44306 NANTES Cedex 03 France Phone: 33 2 40 18 18 18 Fax: +33 2 40 18 19 60
Copyright TEMIC Semiconductors 1997. Copyright INTEL Corporation 1994. Portions reprinted by permission of INTEL Corporation.
Rev. C - May 7, 1999
TSC80251
Table of Contents
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1
1.1. Extended 8-bit Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 1.2. TSC80251 Derivatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 1.3. TSC80251 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3
Chapter 2: Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1
2.1. Microcontroller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 2.2. Microcontroller Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2
2.2.1. CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 2.2.2. Clock and Reset Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 2.2.3. Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4
Chapter 3: Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1
3.1. C251 Architecture Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2. C51 Architecture Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 3.3. C51 Architecture mapping to C251 Architecture Address Spaces . . . . . . . . . . . . . . . 3.2 3.4. TSC80251 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4
3.4.1. Byte, Word and Dword Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2. Dedicated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2.1. Accumulator and B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2.2. Extended Data Pointer, DPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2.3. Extended Stack Pointer, SPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 3.6 3.7 3.7 3.7
3.5. Special Function Registers (SFRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9
Chapter 4: Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1
4.1. Source Mode or Binary Mode Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1
4.1.1. Selecting Binary Mode or Source Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2
4.2. Programming Features of the C251 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2
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TSC80251
4.2.1. Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1.1. Order of Byte Storage for Words and Double Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2. Register Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3. Address Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4. Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 4.3 4.3 4.3 4.4
4.3. Program Status Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 4.4. Data Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5
4.4.1. Data Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.1. Addressable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.2. Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.3. Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.4. Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.5. Displacement Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4. Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 4.5 4.6 4.6 4.6 4.8 4.8 4.8 4.9
4.5. Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
4.5.1. Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10
4.6. Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11
4.6.1. Addressing Modes for Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2. Conditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3. Unconditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.4. Calls and Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.5. Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.6. Minimum Fixed Interrupt Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.7. Variable Interrupt Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.7.1. Response Time Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.7.2. Computation of Worst Case Latency with Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.8. Latency Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.9. Blocking Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.10. Interrupt Vector Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.11. ISRs in Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 4.12 4.13 4.13 4.14 4.14 4.15 4.15 4.16 4.17 4.17 4.18 4.18
Chapter 5: Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1
5.1. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1
5.1.1. Notation for Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 5.1.2. Size and Execution Time for Instruction Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4
5.2. Opcode Map and SupPorting Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 5.3. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.24
5.3.1. Execution Times for Instructions that Access the Ports SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.24
5.4. Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.36
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . glossary.1
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TSC80251
List of figures
Chapter 2: Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1
Figure 2.1. TSC80251 Product Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Figure 2.2. Central Processor Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Figure 2.3. Clocking Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4
Chapter 3: Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1
Figure 3.1. Address Spaces for TSC80251 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Figure 3.2. Address Spaces for the C51 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Figure 3.3. Mappings C51 Architecture to C251 Architecture Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Figure 3.4. TSC80251 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Figure 3.5. Register File in Byte, Word, and Dword Register Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Figure 3.6. Register File Locations 0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Figure 3.7. Dedicated Registers in the Register File and their Corresponding SFRs . . . . . . . . . . . . . . . . . . . . . . . . 3.8
Chapter 4: Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1
Figure 4.1. Binary Mode Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Figure 4.2. Source Mode Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Figure 4.3. Word and Double-word Storage in Big Endian Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Figure 4.4. Interrupt Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Figure 4.5. Response Time Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Figure 4.6. Response Time Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Figure 4.7. Program Status Word register (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Figure 4.8. Program Status Word 1 register (PSW1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20
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List of tables
Chapter 3: Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1
Table 3.1. Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2. Register Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.3. Dedicated Registers in the Register File and their Corresponding SFRs . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.4. Core SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 3.4 3.6 3.9
Chapter 4: Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1
Table 4.1. Examples of Opcodes in Binary and Source Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Table 4.2. Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Table 4.3. Notation for Byte Registers, Word Registers, and Dword Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Table 4.4. The Efffects of Instructions on the PSW and PSW1 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Table 4.5. Addressing Modes for Data Instruction in the C51 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Table 4.6. Addressing Modes for Data Instruction in the C251 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Table 4.7. Bit-addressable Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Table 4.8. Two Samples of Bits Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Table 4.9. Addressing Modes for Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Table 4.10. Addressing Modes for Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Table 4.11. Compare-conditional Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Table 4.12. Interrupt Latency Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Table 4.13. Actual vs. Predicted Latency Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17
Chapter 5: Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1
Table 5.1. Minimum Number of States per Instruction for given Average Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Table 5.2. Notation for Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Table 5.3. Notation for Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Table 5.4. Notation for Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Table 5.5. Notation for Destination in Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Table 5.6. Notation for Register Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Table 5.7. Summary of Add and Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Table 5.8. Summary of Increment and Decrement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Table 5.9. Summary of Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Table 5.10. Summary of Logical Instructions (1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Table 5.11. Summary of Logical Instructions (2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Table 5.12. Summary of Multiply, Divide and Decimal-adjust Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Table 5.13. Summary of Move Instructions (1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Table 5.14. Summary of Move Instructions (2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Table 5.15. Summary of Move Instructions (3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Table 5.16. Summary of Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Table 5.17. Summary of Exchange, Push and Pop Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Table 5.18. Summary of Conditional Jump Instructions (1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 Table 5.19. Summary of Conditional Jump Instructions (2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Table 5.20. Summary of unconditional Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 Rev. C - May 7, 1999
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Table 5.21. Summary of Call and Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.22. Instructions for 80C51 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.23. New Instructions for the C251 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.24. Data Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.25. High Nibble, Byte 0 of Data Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.26. Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.27. Byte 1 (High Nibble) for Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.28. PUSH/POP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.29. Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.30. Displacement/Extended MOVs Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.31. INC/DEC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.32. Encoding for INC/DEC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.33. Shifts Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.34. State Times to Access the Port SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.35. Summary of Add and Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.36. Summary of Compare Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.37. Summary of Increment and Decrement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.38. Summary of Multiply, Divide and Decimal-adjust Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.39. Summary of Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.40. Summary of Logical Instructions (Cont'd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.41. Summary of Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.42. Summary of Exchange, Push and Pop Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.43. Summary of Bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.44. Flag Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 5.18 5.19 5.20 5.20 5.21 5.21 5.21 5.22 5.22 5.23 5.23 5.23 5.25 5.27 5.28 5.29 5.29 5.30 5.31 5.31 5.34 5.35 5.36
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Conventions
The following notations and terminology are used in this manual. The Glossary defines all terms with special meanings.
#
The pound symbol (#) has either of two meanings, depending on the context. When used with a signal name, the symbol means that the signal is active low. When used in an instruction, the symbol prefixes an immediate value in immediate addressing mode. Italics identify variables and introduce new terminology. The context in which italics are used distinguishes between two possible meanings. Variables in registers and signal names are commonly represented by x and y, where x represents the first variable and y represents the second variable. For example, in register Px.y, x represents the variable that identifies the specific port, and y represents the register bit variable [7:0]. Variables must be replaced with the correct values when configuring or programming registers or identifying signals. Uppercase X (no italics) represents an unknown value or a "don't care" state or condition. The value may be either binary or hexadecimal, depending on the context. For example, 2XAFh (hex) indicates that bits 11:8 are unknown; 10XXb in binary context indicates that the two Least Significant Bits are unknown.
italics
XXXX
Assert and Deassert The terms Assert and Deassert refer to the act of making a signal active (enabled) and inactive (disabled), respectively. The active polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To assert RD# is to drive it low; to assert ALE is to drive it high; to deassert RD# is to drive it high; to deassert ALE is to drive it low. Instructions Logic 0 (Low) Instruction mnemonics are shown in upper case to avoid confusion. You may use either upper case or lower case. An input voltage level equal to or less than the maximum value of VIL or an output voltage level equal to or less than the maximum value of VOL. See Product Datasheet for values. An input voltage level equal to or greater than the minimum value of VIH or an output voltage level equal to or greater than the minimum value of VOH. See Product Datasheet for values. Hexadecimal numbers are represented by a string of hexadecimal digits followed by the letter h. Decimal and binary numbers are represented by their customary notations: i.e. 255 is a decimal number and 1111 1111 is a binary number. In most cases of binary numbers, the letter b is added for clarity. Bit locations are indexed by 7:0 for byte registers, 15:0 for word registers, and 31:0 for double word (dword) registers. Bit 0 is the least significant bit
Logic 1 (High)
Numbers
Register Bits
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and 7, 15 or 31 are the most significant bits. An individual bit is represented by the register name, followed by a period and the bit number. For example, PCON.4 is bit 4 of the Power Control register. In some discussions, bit names are used. For example, the name of PCON.4 is POF, the Power Off flag. Register Names Register names are shown in upper case. For example, PCON is the Power Control register. If a register name contains a lowercase character, it represents more than one register. For example, CCAPMx (x = 0, 1, 2, 3, 4) represents the five registers: CCAPM0 through CCAPM4. Some registers contain reserved bits. These bits are not used in this device but they may be used in future implementations. Pay attention to the recommendations when manipulating theses bits. The terms Set and Clear refer to the value of a bit or the act of giving it a value. If a bit is Set, its value is "1"; setting a bit gives it a "1" value. If a bit is Clear, its value is "0"; clearing a bit gives it a "0" value.
Reserved Bits
Set and Clear
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Introduction
1.1. 8/16-bit microcontroller
In the world of 8/16-bit microcontrollers, the C51 Architecture has become an industry standard for embedded applications. For over 15 years, TEMIC has been a leading provider of this microcontroller family. This unsurpassed experience is the driving force as TEMIC takes this proven family to the next level of performance: the TSC80251 family! This new C251 Architecture at its lowest performance level (binary mode), is binary code compatible with the 80C51 microcontrollers, hence, attaining an increase in performance has never been easier. Due to a 3-stage pipeline, the CPU-performance is increased by a factor 5, using existing C51 code without modifications. Using the new C251 instruction set, which you will find in this document (See Chapter 5), the performance will increase up to 15 times at the same clock rate. This performance enhancement is based on the 16-bit instruction bus, allowing for more powerful instructions and additional internal instruction bus, 8-bit and 16-bit data busses. The 24-bit address bus will allow to access up to 16 Mbytes in a single linear memory space. Please see each individual TSC80251 Product Design Guide for the effective addressable memory range. Programming flexibility and C-code efficiency are both increased through a Register-based Architecture, the 64-Kbyte extended stack space combining with the new instruction set. C251 C-compilers are some of the most efficient available (nearly no overhead), coupled with the final codesize which could be a factor of 3 down when compared with the C51 C-compilers. All technical information in this document about core features are related to the core revision A and core revision D.
1.2. TSC80251 Derivatives
TEMIC is developing a full family of application specific TSC80251 derivatives. Please see the Design Guide of each product for further information. These products are designed to help you getting high-performance products to market faster. Due to the high instruction throughput, the TSC80251 derivatives are focussing on all high-end 8-bit to 16-bit applications. TSC80251 derivatives are also used in mid-range and lower-end microcontroller applications, where a very low operation frequency is needed, without decreasing the level of CPU-power. This feature is ideal for today portable applications and EMC sensitive systems.
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Typical applications for this family are: D Automotive: G Airbag G ABS G Gearbox G Climate control G Car radio G Car navigation D Communication: G Cordless phones G Cellular phones G High speed modems G High-end feature phones G ISDN phones G Line cards G Network termination D Computer: G High-end monitors G DVD-ROM G Magtape card & smart card readers G Barcodes readers G Computer telephony G Force feedback joysticks D Industrial: G Process monitoring control & readouts G Air conditioning systems G Automation TEMIC's TSC80251 derivatives are designed around the C251 core, using standard peripherals dedicated to a targetted range of applications. Here is a selection of peripheral blocks: D Serial interfaces: G UART (Universal Asynchronous Receiver Transmitter) G I2C (Inter-Integrated Circuit) G SPI (Serial Protocol Interface) G Wire (Synchronous Serial Interface) D Special Functions: G PCA: Programmable Counter Array (5 16-bit modules) G High-speed output G Compare/Capture I/O G 8-bit Pulse Width Modulator (PWM) G ADC (Analog to Digital Converter) G Smart sensor interfaces with PMU (Pulse Measurement Unit) D Control functions: G Watchdog Timer G Timers/Counters G Power monitoring and management G Interrupt handler D Memories: G RAM G ROM G EPROM/OTPROM Most of TEMIC's TSC80251 derivatives are available as ROMless, OTPROM, EPROM and Mask ROM version. For any special request, refer to TEMIC sales representative. 1.2 Rev. C - May 7, 1999
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1.3. TSC80251 Documentation
The following documentation and starter tools are available to allow the full evaluation of the TEMIC's TSC80251 derivatives: D "TSC80251 Programmer's Guide" Contains all information for the programmer (Architecture, Instruction Set, Programming). D "TSC80251 Design Guide" Contains all product specific data and a summary of available application notes. D Application Notes D "TSC80251 Product Starter Kit" This kit enables the product to be evaluated by the designer. Its contents is: G C-Compiler (limited to 2 Kbytes of code) G Assembler G Linker G Product Simulator G TSC80251 Product Evaluation Board with ROM-Monitor G EPROM and ROMless samples of the available derivatives G Please visit our WWW for updated versions in ZIP format. D World Wide Web Please contact our WWW for possible updated information at http://www.temic-semi.com D Technical support: C251@temic-semi.com
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Architectural Overview
2.1. Microcontroller Architecture
The TSC80251 family of 8/16-bit microcontrollers is a high performance upgrade of the widely used 80C51 microcontrollers. It extends features and performance while maintaining binary code compatibility, so the impact on existing hardware and software is minimal. The C251 Architecture core contains: D 24-bit linear addressing and up to 16 Mbytes of memory D a register file based CPU with registers accessible as bytes, words, and double words D a page mode for accelerating external instruction fetches D an instruction pipeline D an enriched instruction set, including 16-bit arithmetic and logic instructions D a 64-Kbyte extended stack space D a minimum instruction-execution time of two clocks (vs. 12 clocks for 80C51 microcontrollers) D binary-code compatibility with 80C51 microcontrollers Several benefits are derived from these features : D preservation of code written for 80C51 microcontrollers D a significant increase in core execution speed in comparison with 80C51 microcontrollers at the same clock rate D support for larger programs and more data D increased efficiency for code written in C language
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Figure 2.1. is a functional block diagram of TSC80251 microcontrollers. The core, which is common to all TSC80251 microcontrollers, is described in the next paragraph. Each derivative in the family has its own on-chip peripherals, I/O Ports, external bus, size of on-chip RAM, type and size of on-chip ROM.
OTPROM EPROM ROM
PORTS
RAM
16-bit Memory Code Peripherals Peripheral Interface Unit 24-bit Data Address Bus 8-bit Data Bus 8-bit Internal Bus 16-bit Memory Address
Bus Interface Unit 24-bit Prog. Counter Bus
16-bit Inst. Bus
Interrupt Handler Unit
CPU
Clock
Reset
Figure 2.1. TSC80251 Product Block Diagram
2.2. Microcontroller Core
The TSC80251 microcontroller core contains the CPU, the clock and reset unit, the interrupt handler, the bus interface and the peripheral interface (See Figure 2.1. ). The CPU contains the instruction sequencer, ALU, register file and data memory interface (See Figure 2.2. ).
2.2.1. CPU
The TSC80251 fetches instructions from on-chip code memory two bytes at a time or from external memory one byte at a time. The instructions are sent over the 16-bit instruction bus to the CPU. You can configure the TSC80251 to operate in page mode for accelerated instruction fetches from external memory. In page mode, if an instruction fetch is to the same 256-byte "page" as the previous fetch, the fetch requires one state (two clocks) rather than two states (four clocks). For information regarding the page or non-page mode selection, see Product Design Guide. The TSC80251 register file has 40 registers, which can be accessed as bytes (8-bit data), words (16-bit data) and double words (32-bit data). As in the C51 Architecture, registers 0-7 consist of four banks of eight registers each, where the active bank is selected by the Program Status Word (PSW) for fast context switches (See "Programming" chapter). 2.2 Rev. C - May 7, 1999
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The TSC80251 CPU is a pipeline machine. When the pipeline is full and code is executing from on-chip code memory, an instruction can be completed every state time. When the pipeline is full and code is executing from external memory (with no wait states and no extension of the ALE signal) an instruction can be completed every two state times.
code 16
address 24
Instruction Sequencer
SRC1 SRC2
8 8
ALU
Register File 16
Data Memory Interface
8 24
data address
Figure 2.2. Central Processor Unit Block Diagram
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2.2.2. Clock and Reset Unit
The timing source for the TSC80251 microcontroller can be an external oscillator or an internal oscillator with an external crystal/resonator. The basic unit of time in TSC80251 is the state time (or state), which is two oscillator periods. The state time is divided into phase P1 and phase P2 (See Figure 2.3. ).
Phase 1 P1 XTAL1
Phase 2 P2
TOSC 2 TOSC = State Time
State 1 P1 P2
State 2 P1 P2
State 3 P1 P2
State 4 P1 P2
State 5 P1 P2
State 6 P1 P2
Figure 2.3. Clocking Definitions
The TSC80251 peripherals operate on a peripheral cycle, which is six state times (this peripheral cycle is not a characteristic of the C251 Architecture). A one-clock interval in a peripheral cycle is denoted by its state and phase (SxPy). For simplicity purpose, XTAL1 signal has been used in this figure. In fact this is the prescaler output that drives the core. The clock prescaler being a software programmable device, the effective core clock can be dynamically adapted to the application speed and power consumption needs. The reset unit places the TSC80251 into a known state. A chip reset is initiated by asserting the RST pin or allowing the Watchdog Timer to time out when the TSC80251 has one.
2.2.3. Interrupt Handler Unit
The Interrupt Handler Unit can receive interrupt requests from many sources: internal peripheral sources, external sources and TRAP instruction. When the interrupt handler grants an interrupt request, the CPU discontinues the normal flow of instructions and branches to a routine that services the source that requested the interrupt. You can enable or disable the interrupts individually (except for TRAP and NMI which cannot be disabled) and you can chose among one to four priority levels for each interrupt.
2.4
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Address Spaces
TSC80251 microcontrollers have three address spaces: a memory space, a Special Function Register (SFR) space and a register file. This chapter describes these address spaces as they apply to all TSC80251 microcontrollers. It also discusses the compatibility of the C251 Architecture and the C51 Architecture in terms of their address spaces.
3.1. C251 Architecture Address Spaces
Figure 3.1. shows the three address spaces: i.e. memory space, SFR space and register file for TSC80251 microcontrollers. The address spaces are depicted as being 8-byte wide with addresses increasing from left to right and from bottom to top (See Figure 3.1. ). Memory Address Space 16 Mbytes FF:FFFFh SFR Space 512 bytes S:1FFh
S:000h
S:007h
Register File space 64 bytes 3Fh 00:0000h 00:0007h 00h 07h
Figure 3.1. Address Spaces for TSC80251 Microcontrollers
It is convenient to view the unsegmented, 16-Mbyte memory space as consisting of 256 64-Kbyte regions, numbered 00: to FF:. Note :
The memory space in the C251 Architecture is unsegmented. The 64- Kbyte "region" 00:, 01:, ..., FF: are introduced only as a convenience for discussions. Addressing in the C251 Architecture is linear; there are no segment registers.
TSC80251 microcontrollers can have up to 64-Kbytes of on-chip code memory in region FF:. On-chip data RAM begins at location 00:0000h. The first 32 bytes (00:0000h-00:001Fh) provide storage for a part of the register file.The sizes of the on-chip code memory and on-chip RAM depend on the particular device. The register file has its own address space (See Figure 3.1. ). The 64 locations in the register file are numbered decimally from 0 to 63. Locations 0-7 represent one of four, switchable register banks, each having 8 registers. The 32 bytes required for these banks occupy locations 00:0000h-00:001Fh in the memory space. Register file locations 8-63 do not appear in the memory space and are new hardware resources of the C251 Architecture. The SFR space can accommodate up to 512 8-bit Special Function Registers with addresses S:000h-S:1FFh. Some of these locations may be unimplemented in a particular device. In the C251 Architecture, the prefix "S:" is used with SFR addresses to distinguish them from the memory space addresses 00:0000h-00:01FFh. Rev. C - May 7, 1999 3.1
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3.2. C51 Architecture Address Spaces
Figure 3.2. shows the address spaces of the C51 Architecture. Internal data memory locations 00h-7Fh can be addressed directly, indirectly by register addressing mode and bit addressing mode for data locations 20h-2Fh. Internal data locations 80h-FFh can only be addressed indirectly. Directly addressing these locations accesses the SFRs. The 64-Kbyte code memory has a separate memory space. Data in the code memory can be accessed only with the MOVC instruction. Similarly, the 64-Kbyte external data memory can be accessed only with the MOVX instruction. The register file (registers R0-R7) comprises four, switchable register banks, each having 8 registers. The 32 bytes required for the four banks occupy locations 00h-1Fh in the on-chip data memory. FFFFh Code (MOVC) 0000h FFFFh External Data (MOVX) 0000h Internal Data FFh (indirect) 80h 7Fh 2Fh R0-R7 R0-R7 R0-R7 R0-R7 1Fh 17h 0Eh 07h register addressable SFRs (direct) FFh
80h 30h 20h Internal Data (direct, indirect) 18h 0Fh 08h 00h
bit addressable
Figure 3.2. Address Spaces for the C51 Architecture
3.3. C51 Architecture mapping to C251 Architecture Address Spaces
The 64-Kbyte code memory for 80C51 microcontrollers maps into region FF: of the memory space for TSC80251 microcontrollers. Assemblers for TSC80251 microcontrollers assemble code for 80C51 microcontrollers into region FF:, and data accesses to code memory (MOVC) are directed to this region. The assembler also maps the interrupt vectors to region FF:. This mapping is transparent to the user; code executes just as with a 80C51 micro without modification.
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Table 3.1. Address Mappings
C51 Architecture Memory Type Code External Data Internal D t It l Data SFRs Register Size 64 Kbytes 64 Kbytes 128 bytes 128 bytes 128 bytes 8 bytes Location 0000h-FFFFh 0000h-FFFFh 00h-7Fh 80h-FFh S:80h-S:FFh R0-R7 Data Addressing Indirect using MOVC Indirect using MOVX Direct, Indirect Indirect Direct Register C251 Architecture Location FF:0000h-FF:FFFFh 01:0000h-01:FFFFh 00:0000h-00:007Fh 00:0080h-00:00FFh S:0080h-S:0FFh 00:0000h-00:001Fh
The 64-Kbyte external data memory for 80C51 microcontrollers is mapped into the memory region specified by bits 16-23 of the data pointer DPX, i.e., DPXL, which is accessible as register file location 57 and also as SFR at S:084h. The reset value of DPXL is 01h, which maps the external memory to region 01: as shown in Figure 3.3. You can change this mapping by writing a different value to DPXL. A mapping of the C51 Architecture external data memory into any 64-Kbyte memory region in the C251 Architecture provides complete runtime compatibility because the lower 16 address bits are identical in both architectures. The 256 bytes of on-chip data memory for 80C51 microcontrollers (00h-FFh) are mapped to addresses 00:0000h-00:00FFh to ensure complete runtime compatibility. In the C51 Architecture, the lower 128 bytes (00h-7Fh) are directly and indirectly addressable; however the upper 128 bytes are accessible by indirect addressing only. In the C251 Architecture, all locations in region 00: are accessible by direct, indirect, and displacement addressing. The 128-byte SFR space for 80C51 microcontrollers is mapped into the 512-byte SFR space of the C251 Architecture starting at address S:080h, as shown in Figure 3.3. This provides complete compatibility with direct addressing of 80C51 microcontroller SFRs (including bit addressing). The SFR addresses are unchanged in the new Architecture. In the C251 Architecture, SFRs, A, B, DPL, DPH and SP, as well as the new DPXL and SPH, reside in the register file for high performance. However, to maintain compatibility, they are also mapped into the SFR space at the same addresses as in the C51 Architecture.
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Memory Address Space 16 Mbytes FFFFh C51 Architecture Code Memory FF:0000h 0000h SFR Space 512 Bytes S:1FFh S:100h C51 Architecture SFRs 80h 02:0000h FFFFh C51 Architecture External Data Memory 01:0000h 0000h FFh C51 Architecture Internal Data Memory 00:0000h 00h 08h C51 Architecture R7 00h R0 Register File. S:000h FFh S:07Fh
Register File 64 Bytes 3Fh
Figure 3.3. Mappings C51 Architecture to C251 Architecture Address Spaces Figure 3.4. TSC80251 Memory Space
3.4. TSC80251 Register File
The TSC80251 register file consists of 40 byte locations: 0-31 and 56-63, as shown in Figure 3.5. These locations are accessible as bits, bytes, words and dwords. Several locations are dedicated to special registers; the others are general-purpose registers. Register file locations 0-7 actually consist of four switchable banks of eight registers each, as illustrated in Figure 3.6. The four banks are implemented as the first 32 bytes of on-chip RAM and are always accessible as locations 00:0000h-00:001Fh in the memory address space. Only one of the four banks is accessible via the register file at a given time. The accessible, or "active", bank is selected by bits RS1 and RS0 in the PSW register, as shown in Table 3.2. This bank selection can be used for fast context switches. Register file locations 8-31 and 56-63 are always accessible. These locations are implemented as registers in the CPU. Register file locations 32-55 are reserved and cannot be accessed.
Table 3.2. Register Bank Selection
PSW Selection Bits Bank Bank 0 Bank 1 Bank 2 Bank 3 3.4 Address Range 00h-07h 08h-0Fh 10h-17h 18h-1Fh RS1 0 0 1 1 RS0 0 1 0 1 Rev. C - May 7, 1999
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3.4.1. Byte, Word and Dword Registers
Depending on its location in the register file, a register is addressable as a byte, a word, or a dword, as shown in the right side of Figure 3.5. A register is named for its lowest numbered byte location. For instance: D R4 is the byte register consisting of location 4. D WR4 is the word register consisting of registers 4 and 5. D DR4 is the dword register consisting of registers 4, 5, 6, and 7. Locations R0-R15 are addressable as bytes, words or dwords. Locations 16-31 are addressable only as words or dwords. Locations 56-63 are addressable only as dwords. Registers are addressed only by the names shown in Figure 3.5. , except for the 32 registers that comprise the four banks of registers R0-R7, which can also be accessed as locations 00:0000h-00:001Fh in the memory space. Byte Registers
Note :
R10 = B R11 = A
56
57
Register File 58 59 60 61
62
63
R8 R0
R9 R10 R11 R12 R13 R14 R15 R1 R2 R3 R4 R5 R6 R7 Word Registers
Locations 32-55 are Reserved
24 16 8 0
25 17 9 1
26 18 10 2
27 19 11 3
28 20 12 4
29 21 13 5
30 22 14 6
31 23 15 7
WR24 WR16 WR8 WR0
WR26 WR18 WR10 WR2
WR28 WR20 WR12 WR4
WR30 WR22 WR14 WR6
Dword Registers DR56 = DPX DR60 = SPX
0
1
2
3 4 5 Banks 0-3
6
7 DR24 DR16 DR8 DR0 DR28 DR20 DR12 DR4
Figure 3.5. Register File in Byte, Word, and Dword Register Views
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Register File 63 Memory Address Space FF:FFFFh
8 0
1
2
3
4
5
6
7
0 0 0 0 1 1 2 1
1 2 2 3
2 3 3 4
3 4 4 5
4 5 5 6
5 6 6 7
6 7 7
7
00:0020h 18h 1Fh 10h 17h 08h 0Fh 00h 07h
Banks 0-3 accessible in memory address space
PSW bits RS1:0 select one bank to be accessed via the register file.
Banks 0-3
Figure 3.6. Register File Locations 0-7
3.4.2. Dedicated Registers
The register file has four dedicated registers : D R10 is the B-register. D R11 is the accumulator (A). D DR56 is the extended data pointer, DPX. D DR60 is the extended stack pointer, SPX. These registers are located in the register file; however, R10, R11 and some bytes of DR56 and DR60 are also accessible as SFRs. The bytes of DPX and SPX can be accessed in the register file only by addressing the dword registers. The dedicated registers in the register file and their corresponding SFRs are illustrated in Figure 3.7. and listed in Table 3.3.
Table 3.3. Dedicated Registers in the Register File and their Corresponding SFRs
Register File Name Stack Pointer (SPX) - - Stack Pointer, High Stack Pointer, Low Data Pointer (DPX) - Data Pointer, Extended Low DPTR Accumulator (A Register) B Register 3.6 Data Pointer, High Data Pointer, Low Mnemonic - - SPH SP - DPXL DPH DPL A B R11 R10 DR56 DR60 Reg. Location 60 61 62 63 56 57 58 59 11 10 SFRs Mnemonic - - SPH SP - DPXL DPH DPL A B Address - - S:BEh S:81h - S:84h S:83h S:82h S:E0h S:F0h
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3.4.2.1. Accumulator and B Register
The 8-bit accumulator (A) is byte register R11, which is also accessible in the SFR space as A at S:0E0h (See Figure 3.7. ). The B register, used in multiplies and divides, is register R10, which is also accessible in the SFR space as B at S:0F0h. Accessing A or B as a register is one state faster than accessing them as SFRs. Instructions in the C51 Architecture use the accumulator as the primary register for data moves and calculations. however, in the C251 Architecture, any of registers R1-R15 can serve for these tasks. As a result, the accumulator does not play the central role that it has in 80C51 microcontrollers.
3.4.2.2. Extended Data Pointer, DPX
Dword register DR56 is the extended data pointer, DPX (See Figure 3.7. ). The lower three bytes of DPX (DPL, DPH and DPXL) are accessible as SFRs. DPL and DPH comprise the 16-bit data pointer DPTR. While instructions in the C51 Architecture always use DPTR as the data pointer, instructions in the C251 Architecture can use any word or dword register as a data pointer. DPXL, the byte in location 57, specifies the region of memory (00:-FF:) that maps into the 64-Kbyte external data memory space in the C51 Architecture. In other words, the MOVX instruction addresses the region specified by DPXL when it moves data to and from external memory. The reset value of DPXL is 01h.
3.4.2.3. Extended Stack Pointer, SPX
Dword register DR60 is the stack pointer, SPX (See Figure 3.7. ). The byte at (location 63) is the 8-bit stack pointer, SP, in the C51 Architecture. The byte at location 62 is the stack pointer high, SPH. The two bytes allow the stack to extend to the top of memory region 00:. SP and SPH can be accessed as SFRs. Two instructions, PUSH and POP directly address the stack pointer. Subroutine calls (ACALL, ECALL, LCALL) and returns (ERET, RET, RETI) also use the stack pointer. To preserve the stack, do not use DR60 as a general-purpose register.
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Register File Stack Pointer, High SPH Stack Pointer SPH SP 60 61 62 63 DR60 = Extended Stack Pointer, SPX SP S:BEh S:81h SFRs
Data Pointer Extended, Low Data Pointer, High Data Pointer, Low DPXL DPH DPL 56 57 58 59 DR56 = Extended Stack Pointer, DPX
DPXL DPH DPL
S:84h S:83h S:82h
R10 B R11 A B A
S:F0h S:E0h
Figure 3.7. Dedicated Registers in the Register File and their Corresponding SFRs
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3.5. Special Function Registers (SFRs)
The Special Function Registers (SFRs) reside in their associated on-chip peripherals or in the core. SFR addresses are preceded by "S:" to differentiate them from addresses in the memory space. Unoccupied locations in the SFR space are unimplemented, i.e., no register exists. If an unimplemented SFR location is read, it returns an unspecified value. Note :
SFRs may be accessed only as bytes; they may not be accessed as words or dwords.
Table 3.4. Core SFRs
Mnemonic A
K
Name Accumulator B register Program Status Word Program Status Word 1 Stack Pointer - LSB of SPX
Address S:E0h S:F0h S:D0h S:D1h S:81h S:BEh - S:82h S:83h S:84h S:A8h S:B1h S:B8h S:B3h S:B7h S:B2h
BK PW PSW1 SP SPH
K K
Stack Pointer high - MSB of SPX Data Pointer (2 bytes) Low Byte of DPTR high Byte of DPTR
K
DPTR DPL K DPH K DPXL IE0 IE1 IPL0 IPL1 IPH0 IPH1
Data Pointer, Extended Low Interrupt Enable Control 0 Interrupt Enable Control 1 Interrupt Priority Control Low 0 Interrupt Priority Control Low 1 Interrupt Priority Control High 0 Interrupt Priority Control High 1
Note: K These SFRs can also be accessed by their corresponding registers in the register file (See Table 3.3.
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Programming
The instruction set for the C251 Architecture is a superset of the instruction set for the C51 Architecture. This chapter describes the addressing modes and summarizes the instruction set, which is divided into data instructions, bit instructions, and control instructions. (Chapter 5, "Instruction Set Reference" contains an opcode map and the detailed description of each instruction.) Notes: D The instruction execution times given in Chapter 5 are for code executing from on-chip code memory and for data that is read from and written to on-chip RAM. Execution times are increased by executing code from external memory, accessing peripheral SFRs, accessing data in external memory, using a wait state, or extending the ALE pulse. D For some instructions, accessing the port SFRs, Px (x = 0, 1, 2, 3) increases the execution time. These cases are noted individually in the tables in Chapter 5.
4.1. Source Mode or Binary Mode Opcodes
Source mode and Binary mode refer to the two ways of assigning opcodes to the instruction set of the C251 Architecture. Depending on the application, one mode or the other may produce more efficient code. The mode is established during device reset based on the value of the SRC bit in configuration byte CONFIG0. For information regarding the configuration bytes, see the Product Design Guide. Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for the C251 Architecture. One of these modes must be selected when the chip is configured. Depending on the application, binary mode or source mode may produce more efficient code. This section describes the binary and source modes and provides some guidelines for selecting the mode for your application. The C251 Architecture has two types of instructions: D Instructions that originate in the C51 Architecture D Instructions that are unique to the C251 Architecture Figure 4.1. shows the opcode map for the binary mode. Area I and area II make up the opcode map for the instructions that are unique to the C251 Architecture. Note that some of these opcodes are reserved for future instructions. The opcode values for areas II and III are identical (06H-FFH). To distinguish between the two areas in binary mode, the opcodes in area III are given the prefix A5H (the A5H instruction is not implemented in the native C51 Architecture). The area III opcodes are thus A506H-A5FFH. Figure 4.2. shows the opcode map for source mode. Areas II and III have switched places (compare with Figure 4.1. ). In source mode, opcodes for instructions in area II require the A5F escape prefix while opcodes for instructions in area III (C251 Architecture) do not. To illustrate the difference between the binary-mode and source-mode opcodes, Table 4.1. shows the opcode assignments for three sample instructions.
Table 4.1. Examples of Opcodes in Binary and Source Modes
Instruction Binary Mode
DEC A SUBB A, R4 SUB R4, R4 14H 9CH A59CH 14CH A59CH 9CH
Opcode Source Mode
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4.1.1. Selecting Binary Mode or Source Mode
If you have code that was written for a C51 microcontroller and you want to run it unmodified on a C251 microcontroller, choose binary mode. You can use the object code without reassembling the source code. You can also assemble the source code with an assembler for the C251 Architecture and have it produce object code that is binary-compatible with C51 microcontrollers. The remainder of this section discusses the selection of binary mode or source mode for code that may contain instructions from both architectures. An instruction with a prefixed opcode requires one more byte for code storage, and if an additional fetch is required for the extra byte, the execution time is increased by one state. This means that using fewer prefixed opcodes produces more efficient code. If a program uses only instructions from the C51 Architecture, the binary-mode code is more efficient because it uses no prefixes. On the other hand, if a program uses many more new instructions than instructions from the C51 Architecture , source mode is likely to produce more efficient code. For a program where the choice is not clear, the better mode can be found by experimenting with a simulator.
A5H Prefix 0H 0H 5H 6H FH 0H 6H FH
I
II
III
FH C51 Architecture C51 Architecture
FH C251 Architecture
Figure 4.1. Binary Mode Opcode Map
A5H Prefix 0H 0H 5H 6H FH 0H 6H FH
I
III
II
FH C51 Architecture C251 Architecture
FH C51 Architecture
Figure 4.2. Source Mode Opcode Map
4.2. Programming Features of the C251 Architecture
The instruction set for TSC80251 microcontrollers provides the user with new instructions that exploit the features of the C251 Architecture while maintaining compatibility with the instruction set for 80C51 microcontrollers. Many of the new instructions can operate on either 8-bit (byte), 16-bit (word) or 32-bit (dword) operands (In comparison with 8-bit and 16-bit operands, 32-bit operands are accessed with fewer addressing modes.). This capability increases the ease and efficiency of programming TSC80251 microcontrollers in a high-level language such as C. The instruction set is divided into "Data Instructions", "Bit Instructions" and "Control Instructions". Data instructions process 8-bit, 16-bit and 32-bit data; bit instructions manipulate bits; and control instructions manage program flow. 4.2 Rev. C - May 7, 1999
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4.2.1. Data Types
Table 4.2. lists the data types that are addressed by the instruction set. Words or dwords (double words) can be stored in memory starting at any byte address; alignment on two-byte or four-byte boundaries is not required. Words and dwords are stored in memory and the register file in big endian form.
Table 4.2. Data Types
Data Type Bit Byte Word Dword (Double Word) Number of Bits 1 8 16 32
4.2.1.1. Order of Byte Storage for Words and Double Words
TSC80251 microcontrollers store words (2 bytes) and double words (4 bytes) in memory and in the register file in big endian form. In memory storage, the most significant byte (MSB) of the word or double word is stored in the memory byte specified in the instruction; the remaining bytes are stored at higher addresses, with the least significant byte (LSB) at the highest address. Words and double words can be stored in memory starting at any byte address. In the register file, the MSB is stored in the lowest byte of the register specified in the instruction. The code fragment in Figure 4.3. illustrates the storage of words and double words in big endian form.
4.2.2. Register Notations
In register-addressing instructions, specific indices denote the registers that can be used in that instruction. For example, the instruction ADD A,Rn uses"Rn" to denote any one of R0, R1, ..., R7; i.e., the range of n is 0-7. The instruction ADD Rm,#data uses "Rm" to denote R0, R1, ..., R15; i.e., the range of m is 0-15. Table 4.3. summarizes the notation used for the register indices. When an instruction contains two registers of the same type (e.g., MOV Rmd,Rms) the first index "d" denotes "destination" and the second index "s" denotes "source".
4.2.3. Address Notations
In the C251 Architecture, memory addresses include a region number (00:, 01:, ..., FF:). SFR addresses have a prefix "S:" (S:000h-S:1FFh). The distinction between memory addresses and SFR addresses is necessary, because memory locations 00:0000h-00:01FFh and SFR locations S:000h-S:1FFh can both be directly addressed in an instruction. 200h 201h A3h 0 A3h 1 B6h 202h B6h 2 3 4 00h 5 00h 6 C4h DR4 7 D7h 203h
WR0
Contents of register file and memory after execution: MOV WR0, #A3B6h MOV 00:0201h, WR0 MOV DR4, #0000C4D7h
Figure 4.3. Word and Double-word Storage in Big Endian Form
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Table 4.3. Notation for Byte Registers, Word Registers, and Dword Registers
Register Type Register Symbol Ri Byte Word Dword Rn Rm WRj DRk Destination Register - - Rmd WRjd DRkd Source Register - - Rms WRjs DRks R0, R1 R0-R7 R0-R15 WR0, WR2, WR4, ..., WR30 DR0, DR4, DR8, ..., DR28,DR56, DR60 Register Range
Instructions in the C51 Architecture use 80h-FFh as addresses for both memory locations and SFRs, because memory locations are addressed only indirectly and SFR locations are addressed only directly. For compatibility, software tools for TSC80251 controllers recognize this notation for instructions in the C51 Architecture. No change is necessary in any code written for 80C51 microcontrollers. For new instructions in the C251 Architecture, the memory region prefixes (00:, 01:, ..., FF:) and the SFR prefix (S:) are required. Also, software tools for the C251 Architecture permit 00: to be used for memory addresses 00h-FFh and permit the prefix S: to be used for SFR addresses in instructions in the C51 Architecture.
4.2.4. Addressing Modes
The C251 Architecture supports the following addressing modes: D Register addressing The instruction specifies the register that contains the operand. D Immediate addressing The instruction contains the operand. D Direct addressing The instruction contains the operand address. D Indirect addressing The instruction specifies the register that contains the operand address. D Displacement addressing The instruction specifies a register and an offset. The operand address is the sum of the register contents (the base address) and the offset. D Relative addressing The instruction contains the signed offset from the next instruction to the target address (the address for transfer of control, e.g., the jump address). D Bit addressing The instruction contains the bit address.
4.3. Program Status Words
The Program Status Word (PSW) register and the Program Status Word 1 (PSW1) register contain four types of bits (See Figure 4.7. and Figure 4.8. ): D CY, AC, OV, N and Z are flags set by hardware to indicate the result of an operation. D The P bit indicates the parity of the accumulator. D Bits RS0 and RS1 are programmed by software to select the active register bank for registers R0-R7. D F0 and UD are available to the user as general-purpose flags. The PSW and PSW1 registers are read/write registers; however, the parity bit in the PSW is not affected by a write. Individual bits can be addressed with the bit instructions ("Bit Instructions"). The PSW and PSW1 bits are used implicitly in the conditional jump instructions ("Conditional Jumps"). 4.4 Rev. C - May 7, 1999
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The PSW register is identical to the PSW register in 80C51 microcontrollers. The PSW1 register exists only in TSC80251 microcontrollers. Bits CY, AC, RS0, RS1, and OV in PSW1 are identical to the corresponding bits in PSW, i.e., the same bit can be accessed in either register. Table 4.4. lists the instructions that affect the CY, AC, OV, N and Z bits.
Table 4.4. The Efffects of Instructions on the PSW and PSW1 Flags
Instruct on Instruction Type Instruction ADD, ADDC, SUB, CMP INC, DEC Arithmetic MUL, DIV (3) DA ANL, ORL, XRL, CLR A, CPL A, RL, RR, SWAP Logical Program g Control C l Notes :
1. X = the flag can be affected by the instruction. 0 = the flag is cleared by the instruction. 2. The AC flag is affected only by operations on 8-bit operands. 3. If the divisor is zero, the OV flag is set, and the other bits are meaningless. 4. For SRL, SLL and SRA instructions, the last bit shifted out is stored in the CY bit.
Flags Affected (1) CY X OV X AC (2) X N X X 0 X X X X X X X X X X Z X X X X X X X X
RLC, RRC, SRL, SLL, SRA (4) CJNE DJNE
4.4. Data Instructions
Data instructions consist of arithmetic, logical, and data-transfer instructions for 8-bit, 16-bit and 32-bit data. This section describes the data addressing modes and the set of data instructions.
4.4.1. Data Addressing Modes
This section describes the data addressing modes, which are summarized in two tables: Table 4.6. for the instructions that are native to the C51 Architecture and Table 4.6. for the data instructions unique to the C251 Architecture. Notes: D References to registers R0-R7, WR0-WR6, DR0 and DR4 always refer to the register bank that is currently selected by the PSW and PSW1 registers. Registers in all banks (active and inactive) can be accessed as memory locations in the range 00h-1Fh. D Instructions from the C51 Architecture access external memory through the region of memory specified by byte DPXL in the extended data pointer register, DPX (DR56). Following reset, DPXL contains 01h, which maps the external memory to region 01:. You can specify a different region by writing to DR56 or the DPXL SFR.
4.4.1.1. Addressable Registers
Both Architectures address registers directly. D C251 Architecture In the register addressing mode, the operand(s) in a data instruction are in byte registers (R0-R15), word registers (WR0, WR2, ..., WR30) or dword registers (DR0, DR4, ..., DR28, DR56, DR60). D C51 Architecture Instructions address registers R0-R7 only. Rev. C - May 7, 1999 4.5
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4.4.1.2. Immediate Addressing
D C251 Architecture In the immediate addressing mode, the instruction contains the data operand itself. Byte operations use 8-bit immediate data (#data); word operations use 16-bit immediate data (#data16). Dword operations use 16-bit immediate data in the lower word and either zeros in the upper word (denoted by #0data16) or ones in the upper word (denoted by #1data16). MOV instructions that place 16-bit immediate data into a dword register (DRk), place the data either into the upper word while leaving the lower word unchanged, or into the lower word with a sign extension or a zero extension. The increment and decrement instructions contain immediate data (#short = 1, 2, or 4), which specifies the amount of the increment/decrement. D C51 Architecture Instructions use only 8-bit immediate data (#data).
4.4.1.3. Direct Addressing
D C251 Architecture In the direct addressing mode, the instruction contains the address of the data operand. The 8-bit direct mode addresses on-chip RAM (dir8 = 00:0000h-00:007Fh) as both bytes and words, and addresses the SFRs (dir8 = S:080h-S:1FFh) as bytes only. The 16-bit direct mode addresses both bytes and words in memory (dir16 = 00:0000h-00:FFFFh). D C51 Architecture The 8-bit direct mode addresses 256 bytes of on-chip RAM (dir8 = 00h-7Fh) as bytes only and the SFRs (dir8 = 80h-FFh) as bytes only.
Table 4.5. Addressing Modes for Data Instruction in the C51 Architecture
Mode Register Immediate Direct Di Address Range of Operand 00h-1Fh Operand in Instruction 00h-7Fh SFRs 00h-FFh Indirect I di t 0000h-FFFFh 0000h-FFFFh Assembly Language Reference R0-R7 (Bank selected by PSW) #data = #00h-#FFh dir8 = 00h-7Fh dir8 = 80h-FFh or SFR mnemonic @R0, @R1 @DPTR, @A+DPTR @A+DPTR, @A+PC On-chip RAM SFR address Accesses on-chip RAM or the lowest 256 bytes of external data memory (MOVX) Accesses external data memory (MOVX) Accesses region FF : of code memory (MOVC) Comments
4.4.1.4. Indirect Addressing
In arithmetic and logical instructions that use indirect addressing, the source operand is always a byte, and the destination is either the accumulator or a byte register (R0-R15). The source address is a byte, word or dword. The two architectures do indirect addressing via different registers: D C251 Architecture Memory is indirectly addressed via word and dword registers : G Word register (@WRj, j = 0, 2, 4, ..., 30) The 16-bit address in WRj can access locations 00:0000h-00:FFFFh. 4.6 Rev. C - May 7, 1999
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G Dword register (@DRk, k = 0, 4, 8, ..., 28, 56, and 60) The 24 least significant bits can access the entire 16-Mbyte address space. The upper eight bits of DRk must be 0. (If you use DR60 as a general data pointer, be aware that DR60 is the extended stack pointer register SPX.) D C51 Architecture Instructions use indirect addressing to access on-chip RAM, code memory, and external data RAM. G Byte register (@Ri, i = 0, 1) Registers R0 and R1 indirectly address on-chip memory locations 00h-FFh and the lowest 256 bytes of external data RAM. G 16-bit data pointer (@DPTR or @A+DPTR) The MOVC and MOVX instructions use these indirect modes to access code memory and external data RAM. G 16-bit program counter (@A+PC) The MOVC instruction uses this indirect mode to access code memory.
Table 4.6. Addressing Modes for Data Instruction in the C251 Architecture
Mode Register Address Range of Operand 00:0000h-00:001Fh Assembly Language Reference R0-R15, WR0-WR30, DR0-DR28, DR56, DR60 #short = 1, 2, or 4 #data8 = #00h-#FFh #data16 = #0000h-#FFFFh dir8 = 00:0000h-00:007Fh dir8 = S:080h-S:1FFh (2) or SFR mnemonic dir16 = 00:0000h-00:FFFFh @WR0-@WR30 @DR0-@DR30, @DR56, @DR60 @WRj +dis16 = @WR0 +0h through @WR30 +FFFFh Upper 8 bits of DRk must be 00h Offset is signed; address wraps around in region 00: On-chip RAM SFR address Comments R0-R7, WR0-WR6, and DR4 are in the register bank currently selected by the PSW and PSW1 Used only in increment and decrement instructions
Immediate 2 bits Immediate 8 bits Immediate 16 bits
N.A. (Operand is in the instruction) N.A. (Operand is in the instruction) N.A. (Operand is in the instruction) 00:0000h-00:007Fh
Direct, 8 address bits Di dd bi
SFRs 00:0000h-00:FFFFh
Direct, 16 address bits Indirect, 16 address bits Indirect, 24 address bits Displacement, 16 address bits Displacement, 24 address bits 00:0000h-00:FFFFh 00:0000h-FF:FFFFh 00:0000h-00:FFFFh
00:0000h-FF:FFFFh
@DRk +dis24 = @DR0 +0h through @DR28 Offset is signed, upper 8 bits of +FFFFh, DRk must 00h @DR56 +(0h-FFFFh), @DR60 +(0h-FFFFh)
Notes: 1. These registers are accessible in the memory space as well as in the register file. 2. The C251 Architecture supports SFRs in locations S:000h-S:1FFh. Rev. C - May 7, 1999 4.7
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4.4.1.5. Displacement Addressing
Several move instructions use displacement addressing to move bytes or words from a source to a destination. Sixteen-bit displacement addressing (@WRj+dis16) accesses indirectly the lowest 64 Kbytes in memory. The base address can be in any word register WRj. The instruction contains a 16-bit signed offset which is added to the base address. Only the lowest 16 bits of the sum are used to compute the operand address. If the sum of the base address and a positive offset exceeds FFFFh, the computed address wraps around within region 00: (e.g. F000h + 2005h becomes 1005h). Similarly, if the sum of the base address and a negative offset is less than zero, the computed address wraps around the top of region 00: (e.g., 2005h + F000h becomes 1005h). 24-bit displacement addressing (@DRk+dis24) accesses indirectly the entire 16-Mbyte address space. The base address must be in DR0, DR4, ..., DR24, DR28, DR56, or DR60. The upper byte in the dword register must be zero. The instruction contains a 16-bit signed offset which is added to the base address.
4.4.2. Arithmetic Instructions
The set of arithmetic instructions is greatly expanded in the C251 Architecture. The ADD and SUB instructions (See Table 5.19) operate on byte and word data that is accessed in several ways : D as the contents of the accumulator, a byte register (Rn), or a word register (WRj) D in the instruction itself (immediate data) D in memory via direct or indirect addressing The ADDC and SUBB instructions are the same as those for 80C51 microcontrollers. The CMP (compare) instruction (See Table 5.20) calculates the difference of two bytes or words and then writes to flags CY, OV, AC, N, and Z in the PSW and PSW1 registers. The difference is not stored. The operands can be addressed in a variety of modes. The most frequent use of CMP is to compare data or addresses preceding a conditional jump instruction. Table 5.21 lists the INC (increment) and DEC (decrement) instructions. The instructions for 80C51 microcontrollers are supplemented by instructions that can address byte, word, and dword registers and increment or decrement them by 1, 2, or 4 (denoted by #short). These instructions are supplied primarily for register-based address pointers and loop counters. The C251 Architecture provides the MUL (multiply) and DIV (divide) instructions for unsigned 8-bit and 16-bit data (Table 5.22). Signed multiply and divide are left for the user to manage through a conversion process. The following operations are implemented : D eight-bit multiplication: 8 bits x 8 bits 16 bits D sixteen-bit multiplication: 16 bits x 16 bits 32 bits D eight-bit division: 8 bits / 8 bits 16 bits (8-bit quotient, 8-bit remainder) D sixteen-bit division: 16 bits / 16 bits 32 bits (16-bit quotient, 16-bit remainder) These instructions operate on pairs of byte registers (Rmd,Rms), word registers (WRjd,WRjs), or the accumulator and B register (A, B). For 8-bit register multiplies, the result is stored in the word register that contains the first operand register. For example, the product from an instruction MUL R3,R8 is stored in WR2. Similarly, for 16-bit multiplies, the result is stored in the dword register that contains the first operand register. For example, the product from the instruction MUL WR6,WR18 is stored in DR4. For 8-bit divides, the operands are byte registers. The result is stored in the word register that contains the first operand register. The quotient is stored in the lower byte, and the remainder is stored in the higher byte. A 16-bit divide is similar. The first operand is a word register, and the result is stored in the double word register that contains that word register. If the second operand (the divisor) is zero, the overflow flag (OV) is set and the other bits in PSW and PSW1 are meaningless.
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4.4.3. Logical Instructions
The C251 Architecture provides a set of instructions that perform logical operations. The ANL, ORL, and XRL (logical AND, logical OR, and logical exclusive OR) instructions operate on bytes and words that are accessed via several addressing modes (See Table 5.23). A byte register, word register, or the accumulator can be logically combined with a register, im-mediate data, or data that is addressed directly or indirectly. These instructions affect the Z and N flags. In addition to the CLR (clear), CPL (complement), SWAP (swap), and four rotate instructions that operate on the accumulator, TSC80251 microcontrollers have three shift commands for byte and word registers : D SLL (Shift Left Logical) shifts the register one bit left and replaces the LSB with 0. D SRL (Shift Right Logical) shifts the register one bit right and replaces the MSB with 0. D SRA (Shift Right Arithmetic) shifts the register one bit right; the MSB is unchanged.
4.4.4. Data Transfer Instructions
Data transfer instructions copy data from one register or memory location to another. These instructions include the move instructions (See Table 5.24) and the exchange, PUSH, and pop instructions (See Table 5.24). Instructions that move only a single bit are listed with the other bit instructions in Table 5.26. MOV (Move) is the most versatile instruction, and its addressing modes are expanded in the C251 Architecture. MOV can transfer a byte, word or dword between any two registers or between a register and any location in the address space. The MOVX (Move External) instruction moves a byte from external memory to the accumulator or from the accumulator to memory. The external memory is in the region specified by DPXL, whose reset value is 01h. The MOVC (Move Code) instruction moves a byte from code memory (region FF:) to the accumulator. MOVS (Move with Sign Extension) and MOVZ (Move with Zero Extension) move the contents of an 8-bit register to the lower byte of a 16-bit register. The upper byte is filled with the sign bit (MOVS) or zeros (MOVZ). The MOVH (Move to high Word) instruction places 16-bit immediate data into the high word of a dword register. The XCH (Exchange) instruction interchanges the contents of the accumulator with a register or memory location. The XCHD (Exchange Digit) instruction interchanges the lower nibble of the accumulator with the lower nibble of a byte in on-chip RAM. XCHD is useful for BCD (binary coded decimal) operations. The PUSH and POP instructions facilitate storing information (PUSH) and then retrieving it (POP) in reverse order. PUSH can push a byte, a word or a dword onto the stack, using the immediate, direct or register addressing modes. POP can pop a byte or a word from the stack to a register or to memory.
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4.5. Bit Instructions
A bit instruction addresses a specific bit in a memory location or SFR. There are four categories of bit instructions: D SETB (Set Bit), CLR (Clear Bit), CPL (Complement Bit). These instructions can set, clear or complement any addressable bit. D ANL (And Logical), ANL/ (And Logical Complement), ORL (OR Logical), ORL/ (Or Logical Complement). These instructions allow anding and oring of any addressable bit or its complement with the CY flag. D MOV (Move) instructions transfer any addressable bit to the carry (CY) bit or vice versa. D Bit-conditional jump instructions execute a jump if the bit has a specified state. The bit-conditional jump instructions are classified with the control instructions.
4.5.1. Bit Addressing
The bits that can be individually addressed are in the on-chip RAM and the SFRs (See Table 4.7. ). The bit instructions that are unique to the C251 Architecture can address a wider range of bits than the instructions from the C51 Architecture. There are some differences in the way the instructions from the two Architectures address bits. In the C51 Architecture, a bit (denoted by bit51) can be specified in terms of its location within a certain register, or it can be specified by a bit address in the range 00h-7Fh. The C251 Architecture does not have bit addresses as such. A bit can be addressed by name or by its location within a certain register, but not by a bit address. Table 4.8. illustrates bit addressing in the two Architectures by using two sample bits: D RAMBIT is bit 5 in RAMREG, which is location 23h. ("RAMBIT" and "RAMREG" are assumed to be defined in user code.) D IT1 is bit 2 in TCON, which is an SFR at location 88h.
Table 4.7. Bit-addressable Locations
Architecture C251 Architecture C51 Architecture Bit-addressable Locations On-chip RAM 20h-7Fh 20h-2Fh All defined SFRs SFRs with addresses ending in 0h or 8h: 80h, 88h, 90h, 98h, ..., F8h SFRs
Table 4.9. lists the addressing modes for bit insructions, and Table 5.26 summarizes the bit instructions. "bit" denotes a bit that is addressed by a new instruction in the C251 Architecture, and "bit51" denotes a bit that is addressed by an instruction in the C51 Architecture.
Table 4.8. Two Samples of Bits Addressing
Location Addressing Mode Register Name On-chip RAM Register Address Bit Name Bit Address Register Name SFR Register Address Bit Name Bit Address 4.10 C51 Architecture RAMREG.5 23h.5 RAMBIT 1Dh TCON.2 88.2h IT1 8A C251 Architecture RAMREG.5 23h.5 RAMBIT NA TCON.2 S:88.2h IT1 NA Rev. C - May 7, 1999
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Table 4.9. Addressing Modes for Bit Instructions
Architecture C251 (bi ) (bit) Variants Memory SFR Memory C51 (bi ) (bit) SFR Bit Address NA NA 00h-7Fh 80h-F8h Memory/SFR Address 20h.0-7Fh.7 All defined SFRs 20h.0-7Fh.7 XXh.0-XXh.7, where XX = 80, 88, 90, 98, ..., F0, F8 SFRs are not defined at all bit-addressable locations Comments
4.6. Control Instructions
Control instructions "instructions that change program flow" include calls, returns, and conditional and unconditional jumps (See Table 5.27). Instead of executing the next instruction in the queue, the processor executes a target instruction. The control instruction provides the address of a target instruction either implicitly, as in a return from a subroutine, or explicitly, in the form of a relative, direct, or indirect address. TSC80251 microcontrollers have a 24-bit program counter (PC), which allows a target instruction to be anywhere in the 16-Mbyte address space. however, as discussed in this section, some control instructions restrict the target address to the current 2-Kbyte or 64-Kbyte address range by allowing only the lowest 11 or lowest 16 bits of the program counter to change.
4.6.1. Addressing Modes for Control Instructions
Table 4.10. lists the addressing modes for the control instructions. D Relative addressing: The control instruction provides the target address as an 8-bit signed offset (rel) from the address of the next instruction. D Direct addressing: The control instruction provides a target address, which can have 11 bits (addr11), 16 bits (addr16), or 24 bits (addr24). The target address is written to the PC. G addr11: Only the lower 11 bits of the PC are changed; i.e., the target address must be in the current 2-Kbyte block (the 2-Kbyte block that includes the first byte of the next instruction). G addr16: Only the lower 16 bits of the PC are changed; i.e., the target address must be in the current 64-Kbyte region (the 64-Kbyte region that includes the first byte of the next instruction). G addr24: The target address can be anywhere in the 16-Mbyte address space. D Indirect addressing: There are two types of indirect addressing for control instructions: G For the instructions LCALL @WRj and LJMP @WRj, the target address is in the current 64-Kbyte region. The 16-bit address in WRj is placed in the lower 16 bits of the PC. The upper eight bits of the PC remain unchanged from the address of the next instruction. G For the instruction JMP @A+DPTR, the sum of the accumulator and DPTR is placed in the lower 16 bits of the PC, and the upper eight bits of the PC are FF:, which restricts the target address to the code memory space of the C51 Architecture.
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Table 4.10. Addressing Modes for Control Instructions
Description Relative, 8-bit relative address (rel) Direct, 11-bit target address (addr11) Direct, 16-bit target address (addr16) Direct, 24-bit target address (addr24) K Indirect (@WRj) K Indirect (@A +DPTR) Note:
K These modes are not used by instructions in the C51 Architecture.
Address Bits Provided 8 11 16 24 16 16
Address Range -128 to +127 from first byte of next instruction Current 2 Kbytes Current 64 Kbytes 00:0000h-FF:FFFFh Current 64 Kbytes 64-Kbyte region specified by DPXL (reset value = 01h)
4.6.2. Conditional Jumps
The C251 Architecture supports bit-conditional jumps, compare-conditional jumps, and jumps based on the value of the accumulator. A bit-conditional jump is based on the state of a bit. In a compare-conditional jump, the jump is based on a comparison of two operands. All conditional jumps are relative, and the target address (rel) must be in the current 256-byte block of code. The instruction set includes three kinds of bit-conditional jumps : D JB (Jump on Bit): Jump if the bit is set. D JNB (Jump on Not Bit): Jump if the bit is clear. D JBC (Jump on Bit then Clear it): Jump if the bit is set; then clear it. Compare-conditional jumps test a condition resulting from a compare (CMP) instruction that is assumed to precede the jump instruction. The jump instruction examines the PSW and PSW1 registers and interprets their flags as though they were set or cleared by a compare (CMP) instruction. Actually, the state of each flag is determined by the last instruction that could have affected that flag. The condition flags are used to test one of the following six relations between the operands : D equal (=), not equal () D greater than (>), less than (<) D greater than or equal (), less than or equal () For each relation there are two instructions, one for signed operands and one for unsigned operands (See Table 4.11. ).
Table 4.11. Compare-conditional Jump Instructions
Operand Type Unsigned Signed JE JNE Relation + u JG JSG t JL JSL JGE JSGE JLE JSLE
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4.6.3. Unconditional Jumps
There are five unconditional jumps. NOP and SJMP jump to addresses relative to the program counter. AJMP, LJMP, and EJMP jump to direct or indirect addresses. D NOP (No Operation) is an unconditional jump to the next instruction. D SJMP (Short Jump) jumps to any instruction within -128 to 127 of the next instruction. D AJMP (Absolute Jump) changes the lowest 11 bits of the PC to jump anywhere within the current 2-Kbyte block of memory. The address can be direct or indirect. D LJMP (Long Jump) changes the lowest 16 bits of the PC to jump anywhere within the current 64-Kbyte region. D EJMP (Extended Jump) changes all 24 bits of the PC to jump anywhere in the 16-Mbyte address space. The address can be direct or indirect.
4.6.4. Calls and Returns
The C251 Architecture provides relative, direct, and indirect calls and returns. D ACALL (Absolute Call) pushes the lower 16 bits of the next instruction address onto the stack and then changes the lower 11 bits of the PC to the 11-bit address specified by the instruction. The call is to an address that is in the same 2-Kbyte block of memory as the address of the next instruction. D LCALL (Long Call) pushes the lower 16 bits of the next-instruction address onto the stack and then changes the lower 16 bits of the PC to the 16-bit address specified by the instruction. The call is to an address in the same 64-Kbyte block of memory as the address of the next instruction. D ECALL (Extended Call) pushes the 24 bits of the next instruction address onto the stack and then changes the 24 bits of the PC to the 24-bit address specified by the instruction. The call is to an address anywhere in the 16-Mbyte memory space. D RET (Return) pops the top two bytes from the stack to return to the instruction following a subroutine call. The return address must be in the same 64-Kbyte region. D ERET (Extended Return) pops the top three bytes from the stack to return to the address following a subroutine call. The return address can be anywhere in the 16-Mbyte address space. D RETI (Return from Interrupt) provides a return from an interrupt service routine. The operation of RETI depends on the INTR bit in the CONFIG1 configuration byte (See Product Design Guide): G For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the following order : PC.7:0, PC.15:8. The RETI instruction pops these two bytes and uses them as the 16-bit return address in region FF:. RETI also restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. G For INTR = 1, an interrupt pushes the three PC bytes and PSW1 onto the stack in the following order: PSW1, PC.23:16, PC.7:0, PC.15:8. The RETI instruction pops these four bytes and then returns to the specified 24-bit address, which can be anywhere in the 16-Mbyte address space. RETI also clears the interrupt request line. (See the note in Table 4.10. regarding compatibility with code written for 80C51 microcontrollers.) The TRAP instruction which caues an interrupt call is useful for the development of emulations of an TSC80251 microcontroller.
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4.6.5. Interrupt Processing
Interrupt processing is a dynamic operation that begins when a source requests an interrupt and lasts until the execution of the first instruction in the interrupt service routine (See Figure 4.4. ). Response time is the amount of time between the interrupt request and the resulting break in the current instruction stream. Latency is the amount of time between the interrupt request and the execution of the first instruction in the interrupt service routine. These periods are dynamic due to the presence of both fixed-time sequences and several variable conditions. These conditions contribute to total elapsed time. Response Time OSC State Time External Interrupt Request Ending Instructions PUSH PC CALL ISR ISR
Latency
Figure 4.4. Interrupt Process
Both response time and latency begin with the request. The subsequent minimum fixed sequence comprises the interrupt sample, poly, and request operations. The variables consist of (but are not limited to): specific instructions in use at request time, internal versus external interrupt source requests, internal versus external program operation, stack location, presence of wait states, page-mode operation and branch pointer length. Note:
In the following discussion external interrupt request pins are assumed to be inactive for at least four state times prior to assertion. In this chapter all external hardware signals maintain some setup period (i.e., less than one state time). Signals must meet VIH and VIL specifications prior to any state time under discussion. This setup state time is not included in examples or calculations for either response or latency.
4.6.6. Minimum Fixed Interrupt Time
All interrupts are sampled or polled every four state times (See Figure 4.4. ). One additional state time is required for a context switch request. For code branches to jump locations in the current 64-Kbyte memory region (compatible with 80C51 microcontrollers), the context switch time is 11 states. Therefore, the minimum fixed poll and request time is 16 states (4 poll states + 1 request state + 11 states for the context switch = 16 state times). Therefore, this minimum fixed period rests upon four assumptions: D The source request is an internal interrupt with high enough priority to take precedence over other potential interrupts. D The request is coincident with internal execution and needs no instruction completion time. D The program uses an internal stack location. D The ISR is in on-chip OTPROM/ROM. 4.14 Rev. C - May 7, 1999
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4.6.7. Variable Interrupt Parameters
Both response time and latency calculations contain fixed and variable components. By definition, it is often difficult to predict exact timing calculations for real-time requests. One large variable is the completion time of an instruction cycle coincident with the occurrence of an interrupt request. Worst-case predictions typically use the longest-executing instruction in an Architecture's code set. In the case of the TSC80251, the longest-executing instruction is a 16-bit divide (DIV). However, even this 21-state instruction may have only 1 or 2 remaining states to complete before the interrupt system injects a context switch. This uncertainty affects both response time and latency.
4.6.7.1. Response Time Variables
Response time is defined as the start of a dynamic time period when a source requests an interrupt and lasts until a break in the current instruction execution stream occurs (See Figure 4.4. ). Response time (and therefore latency) is affected by two primary factors : the incidence of the request relative to the four-state-time sample window and the completion time of instructions in the response period (i.e., shorter instructions complete earlier than longer instructions). Note:
External interrupt signals require one additional state time in comparison to internal interrupts. This is necessary to sample and latch the pin value prior to a poll of interrupts. The sample occurs in the first half of the state time and the poll/request occurs in the second half of the next state time. Therefore, this sample and poll/request portion of the minimum fixed response and latency time is five states for internal interrupts and six states for external interrupts. External interrupts must remain active for at least five state times to guarantee interrupt recognition when the request occurs immediately after a sample has been taken (i.e., requested in the second half of a sample state time).
If the external interrupt goes active one state after the sample state, the pin is not resampled for another three states. After the second sample is taken and the interrupt request is recognized, the interrupt controller requests the context switch. The programmer must also consider the time to complete the instruction at the moment the context switch request is sent to the execution unit. If 9 states of a 10-state instruction have completed when the context switch is requested, the total response time is 6 states, with a context switch immediately after the final state of the 10-state instruction (See Figure 4.5. ).
Response Time = 6 OSC State Time INT0# Sample INT0# Request 10-State Instruction PUSH PC
Figure 4.5. Response Time Example
Conversely, if the external interrupt requests service in the state just prior to the next sample, response is much quicker. One state asserts the request, one state samples, and one state requests the context switch. If at that point the same instruction conditions exist, one additional state time is needed to complete the 10-state instruction prior to the context switch (See Figure 4.6. ). The total response time in this case is four state times. The programmer must evaluate all pertinent conditions for accurate predictability. Rev. C - May 7, 1999 4.15
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Response Time = 4 OSC State Time INT0# Sample INT0# Request 10-State Instruction PUSH PC
Figure 4.6. Response Time Example
4.6.7.2. Computation of Worst Case Latency with Variables
Worst-case latency calculations assume that the longest TSC80251 instruction used in the program must fully execute prior to a context switch. The instruction execution time is reduced by one state with the assumption the instruction state overlaps the request state (therefore, 16-bit DIV is 21 states -1 = 20 states for latency calculations). The calculations add fixed and variable interrupt times (See Table 4.12. ) to this instruction time to predict latency. The worst-case latency (both fixed and variable times included) is expressed by a pseudo-formula : FIXED_TIME + VARIABLES + LONGEST_INSTRUCTION = MAXIMUM LATENCY PREDICTION
Table 4.12. Interrupt Latency Variables
Variable INT0# INT1# T2EX External Execution Page Mode >64 Jump to ISR (1) External Memory Wait State 1 per bus cycle External Stack <64K (1) External Stack >64K (1) External Stack Wait State 1 per bus cycle
Number of States Added Notes:
1
2
1
8
4
8
1. <64K/>64K means inside/outside the 64-Kbyte memory region where code is executing. 2. Base-case fixed time is 16 states and assumes : - a 2-byte instruction is the first ISR byte - Internal execution - <64K jump to ISR - Internal stack - Internal peripheral interrupt
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4.6.8. Latency Calculations
Assume the use of a zero-wait-state external memory where current instructions, the ISR and the stack are located within the same 64-Kbyte memory region (compatible with memory maps for 80C51 microcontrollers.) Further, assume there are 3 states yet to complete in the current 21-state DIV instruction when INT0# requests service. Also assume INT0# has made the request one state prior to the sample state. Unlike in Figure 4.6. , the response time for this assumption is three state times as the current instruction completes in time for the branch to occur. Latency calculations begin with the minimum fixed latency of 16 states. From Table 4.12. , one state is added for an INT0# request from external hardware; two states are added for external execution; and four states for an external stack in the current 64-Kbyte region. Finally, three states are added for the current instruction to complete. The actual latency is 26 states. Worst-case latency calculations predict 43 states for this example due to inclusion of total DIV instruction time (less one state).
Table 4.13. Actual vs. Predicted Latency Calculations
Latency Factors Base Case Minimum Fixed Time INT0# External Request External Execution <64K Byte Stack Location Execution Time for Current (DIV instruction) TOTAL Actual 16 1 2 4 3 26 Predicted 16 1 2 4 20 43
4.6.9. Blocking Conditions
If all enable and priority requirements have been met, a single prioritized interrupt request at a time generates a vector cycle to an interrupt service routine. There are three causes of blocking conditions with hardware-generated vectors : D An interrupt of equal or higher priority level is already in progress (defined as any point after the flag has been set and the RETI of the ISR has not executed). D The current polling cycle is not the final cycle of the instruction in progress. D The instruction in progress is RETI or any write to the IE0, IPH0 or IPL0 registers. Any of these conditions blocks calls to interrupt service routines. Condition two ensures the instruction in progress completes before the system vectors to the ISR. Condition three ensures at least one more instruction executes before the system vectors to additional interrupts if the instruction in progress is a RETI or any write to IE0, IPH0 or IPL0. The complete polling cycle is repeated each four state times.
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4.6.10. Interrupt Vector Cycle
When an interrupt vector cycle is initiated, the CPU breaks the instruction stream sequence, resolves all instruction pipeline decisions, and pushes multiple program counter (PC) bytes onto the stack. The CPU then reloads the PC with a start address for the appropriate ISR. The number of bytes pushed to the stack depends upon the INTR bit in the CONFIG1 configuration register (See Product Design Guide). The complete sample, poll, request and context switch vector sequence is illustrated in the interrupt latency timing diagram. Note:
If the interrupt flag for a level-triggered external interrupt is set but denied for one of the above conditions and is clear when the blocking condition is removed, then the denied interrupt is ignored. In other words, blocked interrupt requests are not buffered for retention.
4.6.11. ISRs in Process
ISR execution proceeds until the RETI instruction is encountered. The RETI instruction informs the processor the interrupt routine is completed. The RETI instruction in the ISR pops PC address bytes off the stack (as well as PSW1 for INTR = 1), and execution resumes at the suspended instruction stream. Note:
A simple RET instruction also returns execution to the interrupted program. In previous implementations this inappropriately allowed the system to operate as though an interrupt service routine is still in progress. The TSC80C251 allow use of both RETI and RET instructions for interrupt completion. However, for code expected to run properly on both 80C51 and TSC80C251 microcontrollers, only the execution of a RETI instruction is considered proper completion of the interrupt operation.
With the exception of TRAP, the start addresses of consecutive interrupt service routines are eight bytes apart. If consecutive interrupts are used (IE0 and TF0, for example, or TF0 and IE1), the first interrupt routine (if more than seven bytes long) must execute a jump to some other memory location. This prevents overlap of the start address of the following interrupt routine.
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PSW (S:D0h) Program Status Word register
CY 7 Bit Number 7 AC 6 Bit Mnemonic CY FO 5 RS1 4 RS0 3 Description Carry flag The carry flag is set by an addition (ADD, ADDC) if there is a carry out of the MSB. It is set by a subtraction (SUB, SUBB) or compare (CMP) if a borrow is needed for the MSB. The carry flag is also affected by some rotate and shift instructions, logical bit instructions and bit move instructions, and the multiply (MUL) and decimal adjust (DA) instructions (See Table 4.4. ). Auxiliary Carry flag The auxiliary flag is affected only by instructions that address 8-bit operands. The AC flag is set if an arithmetic instruction with an 8-bit operand produces a carry out of bit 3 (from addition) or a borrow into bit 3 (from subtraction). Otherwise it is cleared. This flag is useful for BCD arithmetic (See Table 4.4. ). Flag 0 This general-purpose flag is available to the user. Register Bank Select bit 1 This bit selects the memory locations that comprise the active bank of the register file (registers R0-R7). RS1 Bank Address 0 0 00h-07h 0 1 08h-0Fh 1 2 10h-17h 1 3 18h-1Fh Register Bank Select bit 0 This bit selects the memory locations that comprise the active bank of the register file (registers R0-R7). RS0 Bank Address 0 0 00h-07h 1 1 08h-0Fh 0 2 10h-17h 1 3 18h-1Fh Overflow flag This bit is set if an addition or subtraction of signed variables results in an overflow error (i.e., if the magnitude of the sum or differnecce is too great for the seven LSBs in 2's-complement representation). The overflow flag is also set if a multiplication product overflows one byte or if a division by zero is attempted. User-definable flag This general-purpose flag is available to the user. Parity bit This bit indicates the parity of the accumulator. It is set if an odd number of bits in the accumulator are set. Otherwise, it is cleared. Not all instructions update the parity bit. OV 2 UD 1 P 0
6
AC
5 4
FO RS1
3
RS0
2
OV
1 0
UD P
Reset Value = 0000 0000b
Figure 4.7. Program Status Word register (PSW)
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PSW1 (S:D1h) Program Status Word 1 register
CY 7 Bit Number 7 6 5 AC 6 Bit Mnemonic CY AC N N 5 RS1 4 RS0 3 Description Carry flag Identical to the CY bit in the PSW register (See Figure 4.7. ). Auxiliary Carry flag Identical to the AC bit in the PSW register (See Figure 4.7. ). Negative flag This bit is set if the result of the last logical or arithmetic operation was negative, i.e., bit15 = 1. Otherwise it is cleared. Register Bank Select bit 1 Identical to the RS1 bit in the PSW register (See Figure 4.7. ). Register Bank Select bit 0 Identical to the RS0 bit in the PSW register (See Figure 4.7. ). Overflow flag Identical to the OV bit in the PSW register (See Figure 4.7. ). Zero flag This flag is set if the result of the last logical or arithmetic operation is zero. Otherwise it is cleared. Reserved The value read from this bit is indeterminate. Do not set this bit. OV 2 Z 1 - 0
4 3 2 1
RS1 RS0 OV Z
0
-
Reset Value = 0000 0000b
Figure 4.8. Program Status Word 1 register (PSW1)
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Instruction Set Reference
This chapter contains reference material for the instructions in the C251 Architecture. It includes an opcode map, a summary of the instructions-with instruction lengths and execution times-and a detailed description of each instruction. It contains the following tables: D Table 5.1. through Table 5.4. describe the notation used for the instruction operands. D Table 5.6. and Table 5.7. comprise the opcode map for the instruction set. D Table 5.8. through Table 5.17. contain supporting material for the opcode map. D Table 5.18. lists execution times for a group of instructions that access the Port SFRs. D The following tables list the instructions with their lengths in bytes and their execution times: G G G G G G G G G Notes:
The instruction execution times given in this appendix are for code executing from on-chip code memory and for data that is read from and written to on-chip RAM. Execution times are increased by executing code from external memory, accessing peripheral SFRs, accessing data in external memory, using a wait state, or extending the ALE pulse. For some instructions, accessing the Port SFRs, Px, x = 0-3, increases the execution time.
Add and Subtract Instructions, Table 5.7. Increment and Decrement Instructions, Table 5.8. Compare Instructions, Table 5.9. Logical Instructions, Table 5.10. to Table 5.11. Multiply, Divide and Decimal-adjust Instructions, Table 5.12. Move Instructions, Table 5.13. to Table 5.15. Bit Instructions, Table 5.16. Exchange, Push and Pop Instructions, Table 5.17. Control Instructions, Table 5.29.
5.1. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are two concurrent processes limiting the effective instruction throughput: D Instruction Fetch D Instruction Execution Table 5.7. to Table 5.21. assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and this is never limiting the execution speed. If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited depending on the average size of instructions (for the considered section of the program flow). The maximum average instruction throughput is provided by Table 5.1. depending on the external memory configuration (from Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer values.
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Table 5.1. Minimum Number of States per Instruction for given Average Sizes Average size of Instructions (bytes) 1 2 3 4 5 Non-Page Mode (states) 0 Wait State 2 4 6 8 10 1 Wait State 3 6 9 12 15 2 Wait States 4 8 12 16 20 3 Wait States 5 10 15 20 25 4 Wait States 6 12 18 24 30 Page Mode (states) 1 2 3 4 5
If the average execution time of the considered instructions is larger than the number of states given by Table 5.1. , this larger value will prevail as the limiting factor. Otherwise, the value from Table 5.1. must be taken. This is providing a fair estimation of the execution speed but only the actual code execution can provide the final value.
5.1.1. Notation for Instruction Operands
Table 5.2. to Table 5.6. provide Notation for Instruction Operands. Table 5.2. Notation for Direct Addressing Direct Address dir8 Description A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address (80h-FFh). It is a byte (default), word or double word depending on the other operand. A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing. Table 5.3. Notation for Immediate Addressing Immediate Address #data #data16 #0data16 #1data16 #short Description An 8-bit constant that is immediately addressed in an instruction A 16-bit constant that is immediately addressed in an instruction A 32-bit constant that is immediately addressed in an instruction. The upper word is filled with zeros (#0data16) or ones (#1data16). A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction. Table 5.4. Notation for Bit Addressing Direct Address bit51 Description A directly addressed bit (bit number= 00h-FFh) in memory or an SFR. Bits 00h-7Fh are the 128 bits in byte locations 20h-2Fh in the on-chip RAM. Bits 80h-FFh are the 128 bits in the 16 SFRs with addresses that end in 0h or 8h, S:80h, S:88h, S:90h,..., S:F0h, S:F8h. A directly addressed bit in memory locations 00:0020h-00:007Fh or in any defined SFR. C251 C51 n n C251 n n n n C51 n C251 n C51 n
dir16
n
bit
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Table 5.5. Notation for Destination in Control Instructions Direct Address rel addr11 addr16 addr24 Description A signed (two's complement) 8-bit relative address. The destination is -128 to +127 bytes relative to the next instruction's first byte. An 11-bit target address. The target is in the same 2-Kbyte block of memory as the next instruction's first byte. A 16-bit target address. The target can be anywhere within the same 64-Kbyte region as the next instruction's first byte. A 24-bit target address. The target can be anywhere within the 16-Mbyte address space. n C251 n C51 n n n
Table 5.6. Notation for Register Operands Register @Ri Rn n Rm Rmd Rms m, md, ms WRj WRjd WRjs @WRj @WRj +dis16 j, jd, js Description A memory location (00h-FFh) addressed indirectly via byte registers R0 or R1 Byte register R0-R7 of the currently selected register bank Byte register index: n= 0-7 Byte register R0-R15 of the currently selected register file Destination register Source register Byte register index: m, md, ms= 0-15 Word register WR0, WR2, ..., WR30 of the currently selected register file Destination register Source register A memory location (00:0000h-00:FFFFh) addressed indirectly through word register WR0-WR30, is the target address for jump instructions. A memory location (00:0000h-00:FFFFh) addressed indirectly through word register (WR0-WR30) + 16-bit signed (two's complement) displacement value Word register index: j, jd, js= 0-30 Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently selected register file Destination register Source register A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register DR0-DR28, DR56 and DR60, is the target address for jump instruction A memory location (00:0000h-FF:FFFFh) addressed indirectly through dword register (DR0-DR28, DR56, DR60) + 16-bit (two's complement) signed displacement value Dword register index: k, kd, ks= 0, 4, 8..., 28, 56, 60 n C251 C51 n n
n
DRk DRkd DRks @DRk @DRk +dis16 k, kd, ks
n
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5.1.2. Size and Execution Time for Instruction Families
Table 5.7. Summary of Add and Subtract Instructions Add Subtract Add with Carry Subtract with Borrow Mnemonic , (1) A, Rn ADD A, dir8 A, @Ri A, #data Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 ADD / SUB Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk A, Rn ADDC / SUBB A, dir8 A, @Ri A, #data Register to ACC Direct address to ACC Indirect address to ACC Immediate data to ACC Byte register to/from byte register Word register to/from word register Dword register to/from dword register Immediate 8-bit data to/from byte register Immediate 16-bit data to/from word register 16-bit unsigned immediate data to/from dword register Direct address (on-chip RAM or SFR) to/from byte register Direct address (on-chip RAM or SFR) to/from word register Direct address (64K) to/from byte register Direct address (64K) to/from word register Indirect address (64K) to/from byte register Indirect address (16M) to/from byte register Register to/from ACC with carry Direct address (on-chip RAM or SFR) to/from ACC with carry Indirect address to/from ACC with carry Immediate data to/from ACC with carry ADD , SUB , ADDC , SUBB , Comments dest opnd dest opnd + src opnd dest opnd dest opnd - src opnd (A) (A) + src opnd + (CY) (A) (A) - src opnd - (CY) Binary Mode Bytes 1 2 1 2 3 3 3 4 5 5 4 4 5 5 4 4 1 2 1 2 States 1 1(2) 2 1 2 3 5 3 4 6 3(2) 4 3(3) 4(4) 3(3) 4(3) 1 1(2) 2 1 Source Mode Bytes 2 2 2 2 2 2 2 3 4 4 3 3 4 4 3 3 2 2 2 2 States 2 1(2) 3 1 1 2 4 2 3 5 2(2) 3 2(3) 3(4) 2(3) 3(3) 2 1(2) 3 1
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 4. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
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Table 5.8. Summary of Increment and Decrement Instructions Increment Increment Decrement Decrement Mnemonic A INC DEC Rn dir8 @Ri INC DEC INC DEC INC Rm, #short WRj, #short DRk, #short DRk, #short DPTR , (1) ACC by 1 Register by 1 Direct address (on-chip RAM or SFR) by 1 Indirect address by 1 Byte register by 1, 2, or 4 Word register by 1, 2, or 4 Double word register by 1, 2, or 4 Double word register by 1, 2, or 4 Data pointer by 1 INC INC , DEC DEC , Comments dest opnd dest opnd + 1 dest opnd dest opnd + src opnd dest opnd dest opnd - 1 dest opnd dest opnd - src opnd Binary Mode Bytes 1 1 2 1 3 3 3 3 1 States 1 1 2(2) 3 2 2 4 5 1 Source Mode Bytes 1 2 2 2 2 2 2 2 1 States 1 2 2(2) 4 1 1 3 4 1
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 5.9. Summary of Compare Instructions Compare Mnemonic , (1) Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 DRk, #1data16 CMP Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk CMP , Comments Register with register Word register with word register Dword register with dword register Register with immediate data Word register with immediate 16-bit data Dword register with zero-extended 16-bit immediate data Dword register with one-extended 16-bit immediate data Direct address (on-chip RAM or SFR) with byte register Direct address (on-chip RAM or SFR) with word register Direct address (64K) with byte register Direct address (64K) with word register Indirect address (64K) with byte register Indirect address (16M) with byte register dest opnd - src opnd Binary Mode Bytes 3 3 3 4 5 5 5 4 4 5 5 4 4 States 2 3 5 3 4 6 6 3(1) 4 3(2) 4(3) 3(2) 4(2) Source Mode Bytes 2 2 2 3 4 4 4 3 3 4 4 3 3 States 1 2 4 2 3 5 5 2(1) 3 2(2) 3(3) 2(2) 3(2)
Notes: 1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
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Table 5.10. Summary of Logical Instructions (1/2) Logical AND(1) Logical OR(1) Logical Exclusive OR(1) Clear(1) Complement(1) Rotate Left Rotate Left Carry ANL , ORL , XRL , CLR A CPL A RL A RLC A dest opnd dest opnd src opnd dest opnd dest opnd V src opnd dest opnd dest opnd src opnd (A) 0 (A) (A) (A)n+1 (A)n, n= 0..6 (A)0 (A)7 (A)n+1 (A)n, n= 0..6 (CY) (A)7 (A)0 (CY) (A)n-1 (A)n, n= 7..1 (A)7 (A)0 (A)n-1 (A)n, n= 7..1 (CY) (A)0 (A)7 (CY) Binary Mode Bytes 1 2 1 2 2 3 3 3 4 5 4 4 5 5 4 4 1 1 1 1 1 1 States 1 1(3) 2 1 2(4) 3(4) 2 3 3 4 3(3) 4 3(5) 4(6) 3(5) 4(5) 1 1 1 1 1 1 Source Mode Bytes 2 2 2 2 2 3 2 2 3 4 3 3 4 4 3 3 1 1 1 1 1 1 States 2 1(3) 3 1 2(4) 3(4) 1 2 2 3 2(3) 3 2(5) 3(6) 2(5) 3(5) 1 1 1 1 1 1
Rotate Right Rotate Right Carry
RR A RRC A
Mnemonic
, (2) A, Rn A, dir8 A, @Ri A, #data dir8, A dir8, #data Rmd, Rms WRjd, WRjs Rm, #data WRj, #data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk A A A A A A
Comments register to ACC Direct address (on-chip RAM or SFR) to ACC Indirect address to ACC Immediate data to ACC ACC to direct address Immediate 8-bit data to direct address Byte register to byte register Word register to word register Immediate 8-bit data to byte register Immediate 16-bit data to word register Direct address to byte register Direct address to word register Direct address (64K) to byte register Direct address (64K) to word register Indirect address (64K) to byte register Indirect address (16M) to byte register Clear ACC Complement ACC Rotate ACC left Rotate ACC left through CY Rotate ACC right Rotate ACC right through CY
ANL ORL XRL
CLR CPL RL RLC RR RRC
Notes: 1. Logical instructions that affect a bit are in Table 5.16. . 2. A shaded cell denotes an instruction in the C51 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. 5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
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Table 5.11. Summary of Logical Instructions (2/2) Shift Left Logical SLL 0 0 n+1 n, n= 0..msb-1 (CY) msb msb msb n-1 n, n= msb..1 (CY) 0 msb 0 n-1 n, n= msb..1 (CY) 0 A3:0 A7:4 Comments Shift byte register left through the MSB Shift word register left through the MSB Shift byte register right Shift word register right Shift byte register left Shift word register left Swap nibbles within ACC Binary Mode Bytes 3 3 3 3 3 3 1 States 2 2 2 2 2 2 2 Source Mode Bytes 2 2 2 2 2 2 1 States 1 1 1 1 1 1 2
Shift Right Arithmetic
SRA
Shift Right Logical
SRL
Swap Mnemonic SLL SRA SRL SWAP Rm WRj Rm WRj Rm WRj A , (1)
SWAP A
Note: 1. A shaded cell denotes an instruction in the C51 Architecture.
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Table 5.12. Summary of Multiply, Divide and Decimal-adjust Instructions Multiply Divide Divide src opnd) opnd src opnd) Decimal-adjust ACC for Addition (BCD) MUL AB MUL , DIV AB DIV , (B:A) (A)x(B) extended dest opnd dest opnd x src opnd (A) Quotient ((A) (B)) (B) Remainder ((A) (B)) ext. dest opnd high Quotient (dest opnd ext. dest opnd low Remainder (dest DA A IF [[(A)3:0 > 9] [(AC)= 1]] THEN (A)3:0 (A)3:0 + 6 !affects CY; IF [[(A)7:4 > 9] [(CY)= 1]] THEN (A)7:4 (A)7:4 + 6 Comments Multiply A and B Multiply byte register and byte register Multiply word register and word register Divide A and B Divide byte register and byte register Divide word register and word register Decimal adjust ACC Binary Mode Bytes 1 3 3 1 3 3 1 States 5 6 12 10 11 21 1 Source Mode Bytes 1 2 2 1 2 2 1 States 5 5 11 10 10 20 1
Mnemonic AB MUL
, (1)
Rmd, Rms WRjd, WRjs AB
DIV
Rmd, Rms WRjd, WRjs
DA
A
Note: 1. A shaded cell denotes an instruction in the C51 Architecture.
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Table 5.13. Summary of Move Instructions (1/3) Move to High word Move with Sign extension Move with Zero extension Move Code Move eXtended Mnemonic MOVH MOVS MOVZ MOVC , (1) DRk, #data16 WRj, Rm WRj, Rm A, @A +DPTR A, @A +PC A, @Ri A, @DPTR @Ri, A @DPTR, A MOVH , MOVS , MOVZ , MOVC A, MOVX , Comments 16-bit immediate data into upper word of dword register Byte register to word register with sign extension Byte register to word register with zeros extension Code byte relative to DPTR to ACC Code byte relative to PC to ACC Extended memory (8-bit address) to ACC(2) Extended memory (16-bit address) to ACC(2) ACC to extended memory (8-bit address)(2) ACC to extended memory (16-bit address)(2) dest opnd31:16 src opnd dest opnd src opnd with sign extend dest opnd src opnd with zero extend (A) src opnd dest opnd src opnd Binary Mode Bytes 5 3 3 1 1 1 1 1 1 States 3 2 2 6(3) 6(3) 4 3(4) 4 4(3) Source Mode Bytes 4 2 2 1 1 1 1 1 1 States 2 1 1 6(3) 6(3) 5 3(4) 4 4(3)
MOVX
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. Extended memory addressed is in the region specified by DPXL (reset value= 01h). 3. If this instruction addresses external memory location, add N+1 to the number of states (N: number of wait states). 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
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Table 5.14. Summary of Move Instructions (2/3) Move(1) Mnemon Mnemoni c , (2) A, Rn A, dir8 A, @Ri A, #data Rn, A Rn, dir8 MOV Rn, #data dir8, A dir8, Rn dir8, dir8 dir8, @Ri dir8, #data @Ri, A @Ri, dir8 @Ri, #data DPTR, #data16 Register to ACC Direct address (on-chip RAM or SFR) to ACC Indirect address to ACC Immediate data to ACC ACC to register Direct address (on-chip RAM or SFR) to register Immediate data to register ACC to direct address Register to direct address Direct address to direct address Indirect address to direct address Immediate data to direct address ACC to indirect address Direct address to indirect address Immediate data to indirect address Load Data Pointer with a 16-bit constant MOV , Comments dest opnd src opnd Binary Mode Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 States 1 1(3) 2 1 1 1(3) 1 2(3) 2(3) 3(4) 3(3) 3(3) 3 3(3) 3 2 Source Mode Bytes 2 2 2 2 2 3 3 2 3 3 3 3 2 3 3 3 States 2 1(3) 3 1 2 2(3) 2 2(3) 3(3) 3(4) 4(3) 3(3) 4 4(3) 4 2
Notes: 1. Instructions that move bits are in Table 5.16. . 2. Move instructions from the C51 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. Apply note 3 for each dir8 operand.
Table 5.15. Summary of Move Instructions (3/3) Move(1) Mnemonic MOV , , (2) Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 DRk, #1data16 Rm, dir8 WRj, dir8 5.10 Comments Byte register to byte register Word register to word register Dword register to dword register Immediate 8-bit data to byte register Immediate 16-bit data to word register zero-ext 16bit immediate data to dword register one-ext 16bit immediate data to dword register Direct address to byte register Direct address to word register dest opnd src opnd Binary Mode Bytes 3 3 3 4 5 5 5 4 4 States 2 2 3 3 3 5 5 3(3) 4 Source Mode Bytes 2 2 2 3 4 4 4 3 3 States 1 1 2 2 2 4 4 2(3) 3
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Mnemonic , (2) DRk, dir8 Rm, dir16 WRj, dir16 DRk, dir16 Rm, @WRj Rm, @DRk WRjd, @WRjs WRj, @DRk dir8, Rm MOV dir8, WRj dir8, DRk dir16, Rm dir16, WRj dir16, DRk @WRj, Rm @DRk, Rm @WRjd, WRjs @DRk, WRj Rm, @WRj +dis16 WRj, @WRj +dis16 Rm, @DRk +dis24 WRj, @WRj +dis24 @WRj +dis16, Rm @WRj +dis16, WRj @DRk +dis24, Rm @DRk +dis24, WRj Comments Direct address to dword register Direct address (64K) to byte register Direct address (64K) to word register Direct address (64K) to dword register Indirect address (64K) to byte register Indirect address (16M) to byte register Indirect address (64K) to word register Indirect address (16M) to word register Byte register to direct address Word register to direct address Dword register to direct address Byte register to direct address (64K) Word register to direct address (64K) Dword register to direct address (64K) Byte register to indirect address (64K) Byte register to indirect address (16M) Word register to indirect address (64K) Word register to indirect address (16M) Indirect with 16-bit dis (64K) to byte register Indirect with 16-bit dis (64K) to word register Indirect with 16-bit dis (16M) to byte register Indirect with 16-bit dis (16M) to word register Byte register to indirect with 16-bit dis (64K) Word register to indirect with 16-bit dis (64K) Byte register to indirect with 16-bit dis (16M) Word register to indirect with 16-bit dis (16M) Binary Mode Bytes 4 5 5 5 4 4 4 4 4 4 4 5 5 5 4 4 4 4 5 5 5 5 5 5 5 5 States 6 3(4) 4(5) 6(6) 3(4) 4(4) 4(5) 5(5) 4(3) 5 7 4(4) 5(5) 7(6) 4(4) 5(4) 5(5) 6(5) 6(4) 7(5) 7(4) 8(5) 6(4) 7(5) 7(4) 8(5) Source Mode Bytes 3 4 4 4 3 3 3 3 3 3 3 4 4 4 3 3 3 3 4 4 4 4 4 4 4 4 States 5 2(4) 3(5) 5(6) 2(4) 3(4) 3(5) 4(5) 3(3) 4 6 3(4) 4(5) 6(6) 3(4) 4(4) 4(5) 5(5) 5(4) 6(5) 6(4) 7(5) 5(4) 6(5) 6(4) 7(5)
Notes: 1. Instructions that move bits are in Table 5.16. . 2. Move instructions unique to the C251 Architecture. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states). 5. If this instruction addresses external memory location, add 2(N+1) to the number of states (N: number of wait states). 6. If this instruction addresses external memory location, add 4(N+2) to the number of states (N: number of wait states).
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Table 5.16. Summary of Bit Instructions Clear Bit CLR Set Bit SETB Complement Bit CPL AND Carry with Bit ANL CY, AND Carry with Complement of Bit (CY) (CY) src opnd OR Carry with Bit ORL CY, OR Carry with Complement of Bit (CY) (CY) src opnd Move Bit to Carry MOV CY, Move Bit from Carry MOV , CY Mnemonic CY CLR bit51 bit CY SETB bit51 bit CY CPL bit51 bit CY, bit51 ANL CY, bit CY, /bit51 CY, /bit CY, bit51 ORL CY, bit CY, /bit51 CY, /bit CY, bit51 MOV CY, bit bit51, CY bit, CY , (1) Clear carry Clear direct bit Clear direct bit Set carry Set direct bit Set direct bit Complement carry Complement direct bit Complement direct bit And direct bit to carry And direct bit to carry And complemented direct bit to carry And complemented direct bit to carry Or direct bit to carry Or direct bit to carry Or complemented direct bit to carry Or complemented direct bit to carry Move direct bit to carry Move direct bit to carry Move carry to direct bit Move carry to direct bit Comments dest opnd 0 dest opnd 1 dest opnd bit (CY) (CY) src opnd ANL CY, / (CY) (CY) src opnd ORL CY, / (CY) src opnd dest opnd (CY) Binary Mode Bytes 1 2 4 1 2 4 1 2 4 2 4 2 4 2 4 2 4 2 4 2 4 States 1 2(3) 4(3) 1 2(3) 4(3) 1 2(3) 4(3) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 1(2) 3(2) 2(3) 4(3) Source Mode Bytes 1 2 3 1 2 3 1 2 3 2 3 2 3 2 3 2 3 2 3 2 3 States 1 2(3) 3(3) 1 2(3) 3(3) 1 2(3) 3(3) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 1(2) 2(2) 2(3) 3(3)
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
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Table 5.17. Summary of Exchange, Push and Pop Instructions Exchange bytes Exchange Digit Push Pop , (1) A, Rn XCH A, dir8 A, @Ri XCHD A, @Ri dir8 #data #data16 PUSH Rm WRj DRk dir8 POP Rm WRj DRk XCH A, XCHD A, PUSH POP (A) $ src opnd (A)3:0 $ src opnd3:0 (SP) (SP) +1; ((SP)) src opnd; (SP) (SP) + size (src opnd) - 1 (SP) (SP) - size (dest opnd) + 1; dest opnd ((SP)); (SP) (SP) -1 Comments ACC and register ACC and direct address (on-chip RAM or SFR) ACC and indirect address ACC low nibble and indirect address (256 bytes) Push direct address onto stack Push immediate data onto stack Push 16-bit immediate data onto stack Push byte register onto stack Push word register onto stack Push double word register onto stack Pop direct address (on-chip RAM or SFR) from stack Pop byte register from stack Pop word register from stack Pop double word register from stack Binary Mode Bytes 1 2 1 1 2 4 5 3 3 3 2 3 3 3 States 3 3(3) 4 4 2(2) 4 5 4 5 9 3(2) 3 5 9 Source Mode Bytes 2 2 2 2 2 3 4 2 2 2 2 2 2 2 States 4 3(3) 5 5 2(2) 3 5 3 4 8 3(2) 2 4 8
Mnemonic
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
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Table 5.18. Summary of Conditional Jump Instructions (1/2) Jump conditional on status , (1) rel rel rel rel rel rel rel rel rel rel Jcc rel (PC) (PC) + size (instr); IF [cc] THEN (PC) (PC) + rel Comments Jump if carry Jump if not carry Jump if equal Jump if not equal Jump if greater than Jump if less than, or equal Jump if less than (signed) Jump if less than, or equal (signed) Jump if greater than (signed) Jump if greater than or equal (signed) Binary Mode(2) Bytes 2 2 3 3 3 3 3 3 3 3 States 1/4(3) 1/4(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) 2/5(3) Source Mode(2) Bytes 2 2 2 2 2 2 2 2 2 2 States 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3) 1/4(3)
Mnemonic JC JNC JE JNE JG JLE JSL JSLE JSG JSGE
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. States are given as jump not-taken/taken. 3. In internal execution only, add 1 to the number of states of the `jump taken' if the destination address is internal and odd.
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Table 5.19. Summary of Conditional Jump Instructions (2/2) (PC) (PC) + size (instr); IF [src opnd= 1] THEN (PC) (PC) + rel Jump if not bit JNB , rel (PC) (PC) + size (instr); IF [src opnd= 0] THEN (PC) (PC) + rel Jump if bit and clear JBC , rel (PC) (PC) + size (instr); IF [dest opnd= 1] THEN dest opnd 0 (PC) (PC) + rel Jump if accumulator is zero JZ rel (PC) (PC) + size (instr); IF [(A)= 0] THEN (PC) (PC) + rel Jump if accumulator is not zero JNZ rel (PC) (PC) + size (instr); IF [(A) 0] THEN (PC) (PC) + rel Compare and jump if not equal CJNE , , rel (PC) (PC) + size (instr); IF [src opnd1 < src opnd2] THEN (CY) 1 IF [src opnd1 src opnd2] THEN (CY) 0 IF [src opnd1 src opnd2] THEN (PC) (PC) + rel Decrement and jump if not zero DJNZ , rel (PC) (PC) + size (instr); dest opnd dest opnd -1; IF [ (Z)] THEN (PC) (PC) + rel Jump if bit JB , rel Mnemon Mnemoni c JB , (1) bit51, rel bit, rel bit51, rel bit, rel bit51, rel bit, rel rel rel A, dir8, rel A, #data, rel CJNE Rn, #data, rel @Ri, #data, rel Rn, rel dir8, rel Comments Jump if direct bit is set Jump if direct bit of 8-bit address location is set Jump if direct bit is not set Jump if direct bit of 8-bit address location is not set Jump if direct bit is set & clear bit Jump if direct bit of 8-bit address location is set and clear Jump if ACC is zero Jump if ACC is not zero Compare direct address to ACC and jump if not equal Compare immediate to ACC and jump if not equal Compare immediate to register and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct address and jump if not zero Binary Mode(2) Bytes 3 5 3 5 3 5 2 2 3 3 3 3 2 3 States 2/5(3)(6) 4/7(3)(6) 2/5(3)(6) 4/7(3)(6) 4/7(5)(6) 7/10(5)(6) 2/5(6) 2/5(6) 2/5(3)(6) 2/5(6) 2/5(6) 3/6(6) 2/5(6) 3/6(4)(6) Source Mode(2) Bytes 3 4 3 4 3 4 2 2 3 3 4 4 3 3 States 2/5(3)(6) 3/6(3)(6) 2/5(3)(6) 3/6(3) 4/7(5)(6) 6/9(5)(6) 2/5(6) 2/5(6) 2/5(3)(6) 2/5(6) 3/6(6) 4/7(6) 3/6(6) 3/6(4)(6)
JNB
JBC JZ JNZ
DJNZ
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. States are given as jump not-taken/taken. 3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR. 4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR. 5. If this instruction addresses an I/O Port (Px, x= 0-3), add 3 to the number of states. Add 5 if it addresses a Peripheral SFR. 6. In internal execution only, add 1 to the number of states of the `jump taken' if the destination address is internal and odd.
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Table 5.20. Summary of unconditional Jump Instructions Absolute jump Extended jump opnd Long jump opnd Short jump Jump indirect (DPTR) No operation Mnemonic AJMP EJMP LJMP SJMP JMP NOP , (1) addr11 addr24 @DRk @WRj addr16 rel @A +DPTR AJMP EJMP LJMP SJMP rel JMP @A +DPTR NOP Comments Absolute jump Extended jump Extended jump (indirect) Long jump (indirect) Long jump (direct address) Short jump (relative address) Jump indirect relative to the DPTR No operation (Jump never) (PC) (PC) +2; (PC)10:0 src opnd (PC) (PC) + size (instr); (PC)23:0 src (PC) (PC) + size (instr); (PC)15:0 src (PC) (PC) +2; (PC) (PC) +rel (PC)23:16 FFh; (PC)15:0 (A) + (PC) (PC) +1 Binary Mode Bytes 2 5 3 3 3 2 1 1 States 3(2)(3) 6(2)(4) 7(2)(4) 6(2)(4) 5(2)(4) 4(2)(4) 5(2)(4) 1 Source Mode Bytes 2 4 2 2 3 2 1 1 States 3(2)(3) 5(2)(4) 6(2)(4) 5(2)(4) 5(2)(4) 4(2)(4) 5(2)(4) 1
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. In internal execution only, add 1 to the number of states if the destination address is internal and odd. 3. Add 2 to the number of states if the destination address is external. 4. Add 3 to the number of states if the destination address is external.
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Table 5.21. Summary of Call and Return Instructions Absolute call Extended call Long call Return from subroutine Extended return from subroutine Return from interrupt Trap interrupt ACALL ECALL LCALL RET ERET RETI TRAP (PC) (PC) +2; push (PC)15:0; (PC)10:0 src opnd (PC) (PC) + size (instr); push (PC)23:0; (PC)23:0 src opnd (PC) (PC) + size (instr); push (PC)15:0; (PC)15:0 src opnd pop (PC)15:0 pop (PC)23:0 IF [INTR= 0] THEN pop (PC)15:0 IF [INTR= 1] THEN pop (PC)23:0; pop (PSW1) (PC) (PC) + size (instr); IF [INTR= 0] THEN push (PC)15:0 IF [INTR= 1] THEN push (PSW1); push (PC)23:0 Binary Mode Bytes 2 3 5 3 3 1 3 1 2 States 9(2)(3) 14(2)(3) 14(2)(3) 10(2)(3) 9(2)(3) 7(2) 9(2) 7(2)(4) 12(4) Source Mode Bytes 2 2 4 2 3 1 2 1 1 States 9(2)(3) 13(2)(3) 13(2)(3) 9(2)(3) 9(2)(3) 7(2) 8(2) 7(2)(4) 11(4)
Mnemonic ACALL ECALL LCALL RET ERET RETI TRAP
, (1) addr11 @DRk addr24 @WRj addr16
Comments Absolute subroutine call Extended subroutine call (indirect) Extended subroutine call Long subroutine call (indirect) Long subroutine call Return from subroutine Extended subroutine return Return from interrupt Jump to the trap interrupt vector
Notes: 1. A shaded cell denotes an instruction in the C51 Architecture. 2. In internal execution only, add 1 to the number of states if the destination/return address is internal and odd. 3. Add 2 to the number of states if the destination address is external. 4. Add 5 to the number of states if INTR= 1.
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5.2. Opcode Map and SupPorting Tables
Table 5.22. Instructions for 80C51 Microcontrollers Bin Src 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
K
x0 x0 NOP JBC bit51, rel JB bit51, rel JNB bit51, rel JC rel JNC rel JZ rel JNZ rel SJMP rel MOV DPTR, #data16 ORL CY, bit51 ANL CY, bit51 PUSH dir8 POP dir8 MOVX A, @DPTR MOV @DPTR, A INC A DEC A ADD A, #data ADDC A, #data ORL A, #data ANL A, #data XRL A, #data MOV A, #data DIV A, #data SUBB A, #data MUL AB CJNE A, #data, rel SWAP A DA A CLR A CPL A
x1 x1 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 INC dir8 DEC dir8 ADD A, dir8 ADDC A, dir8 ORL A, dir8 ANL A, dir8 XRL A, dir8 MOV dir8, #data MOV dir8, dir8 SUBB A, dir8 Escape CJNE A, dir8, rel XCH A, dir8 DJNZ A, dir8 MOV A, dir8 MOV dir8, A
x2 x2 LJMP addr16 LCALL addr16 RET RETI ORL dir8, A ANL dir8, A XRL dir8, A ORL CY, bit51 ANL CY, bit51 MOV bit51, CY MOV CY, bit51 CPL bit51 CLR bit51 SETB bit51 MOVX A, @RI MOVX @RI, A INC @Ri DEC @Ri ADD A, @Ri ADDC A, @Ri ORL A, @Ri ANL A, @Ri XRL A, @Ri MOV A, @Ri, data MOV dir8, @Ri SUBB A, @Ri MOV @Ri, dir8 CJNE @Ri, #data, rel XCH A, @Ri XCHD A, @Ri MOV A, @Ri MOV @Ri, A INC Rn DEC Rn ADD A, Rn RR A RRC A RLA RLC A
x3 x3
ORL dir8, #data ANL dir8, #data XRL dir8, #data JMP @A +DPTR MOVC A, @A + PC MOVC A, @A + DPTR INC DPTR CPL CY CLR CY SETB CY
ADDC A, Rn ORL A, Rn ANL A, Rn XRL A, Rn MOV Rn, #data MOV dir8, Rn SUBB A, Rn MOV Rn, dir8 CJNE Rn, #data, rel XCH A, Rn DJNZ Rn, rel MOV A, Rn MOV Rn, A
x takes the values found in Bin and Src column.
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Table 5.23. New Instructions for the C251 Architecture Bin Src 0 1 2 3 4 5 6 7 8 9 A B C D 0 1 2 3 4 5 6 7 8 9 A B Notes :
1. 2. 3. 4. K R = Rm/WRj/DRk. op1, op2 are defined in Table 5.24. SeeTable 5.26. and Table 5.27. See Table 5.28.
A5x8K x8K JSLE rel JSG rel JLE rel JG rel JSL rel JSGE rel JE rel JNE rel
A5x9K x9K MOV Rm, @WRj +dis16 MOV @WRj +dis16, Rm MOV Rm, @DRk +dis24 MOV @DRk +dis24, Rm MOV WRj, @WRj +dis16 MOV @WRj +dis16, WRj MOV WRj, @DRk +dis24 MOV @DRk +dis16, WRj JMP @WRj EJMP @DRk LCALL @WRj ECALL @DRk Escape Bit Instructions (3) TRAP
A5xAK xAK MOVZ WRj, Rm MOVS WRj, Rm
A5xBK xBK INC R, #short (1) MOV reg, ind DEC R, #short (1) MOV ind, reg
MOVZ op1, reg (2) EJMP addr24 ECALL addr24 ERET PUSH op1 (4) MOV DRk, PC POP op1 (4)
ADD Rmd, Rms ORL Rmd, Rms ANL Rmd, Rms XRL Rmd, Rms MOV Rmd, Rms DIV Rmd, Rms SUB Rmd, Rms MUL Rmd, Rms CMP Rmd, Rms
ADD WRjd, WRjs ORL WRjd, WRjs ANL WRjd, WRjs XRL WRjd, WRjs MOV WRjd, WRjs DIV WRjd, WRjs SUB WRjd, WRjs MUL WRjd, WRjs CMP WRjd, WRjs
ADD reg, op2 (2) SLL reg ORL reg, op2 (2) ANL reg, op2 (2) XRL reg, op2 (2) MOV reg, op2 (2) SUB reg, op2 (2) CMP reg, op2 (2)
ADD DRkd, DRks
MOV DRkd, DRks SUB DRkd, DRkd CMP DRkd, DRks
x takes the values found in Bin and Src column.
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Table 5.24. Data Instructions Instruction Oper Rmd, Rms Oper WRjd, WRjs Oper DRkd, DRks Oper Rm, #data Oper WRj, #data16 Oper DRk, #data16 MOV DRk(h), #data16 MOV DRk, #1data16 CMP DRk,#1data16 Oper Rm, dir8 Oper WRj, dir8 Oper DRk, dir8 Oper Rm, dir16 Oper WRj, dir16 Oper DRk, dir16 (1) Oper Rm, @WRj Oper Rm, @DRk x x x x x x 7 7 B x x x x x x x x Byte 0 C D F E E E A E E E E E E E E E E Byte 1 md jd/2 kd/4 m j/2 k/4 k/4 ms js/2 ks/4 0 4 8 C #data #data (high) #data (high) #data (high) #data (low) #data (low) #data (low) Byte 2 Byte 3
m j/2 k/4 m j/2 k/4 m m
1 5 D 3 7 F 9 B
dir8 addr dir8 addr dir8 addr dir16 addr (high) dir16 addr (low) dir16 addr (high) dir16 addr (low) dir16 addr (high) dir16 addr (low) j/2 k/4 0 0
Note : 1. For this instruction, the only valid operation is MOV.
Table 5.25. High Nibble, Byte 0 of Data Instructions x 2 9 B 4 5 6 7 8 A Operation ADD reg, op2 SUB reg, op2 CMP reg, op2 (1) ORL reg, op2 (2) ANL reg, op2 (2) XRL reg, op2 (2) MOV reg, op2 DIV reg, op2 MUL reg, op2 Two modes only: reg op2 = Rmd, Rms Rmd reg, reg, op2 = Wjd, Wjs All data addressing modes are supported. Notes
Notes : 1. The CMP operation does not supPort DRk, direct16. 2. For the ORL, ANL and XRL operations, neither reg nor op2 can be DRk.
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All of the bit instructions in the C251 Architecture (See Table 5.23. ) have opcode A9, which serves as an escape byte (similar to A5). The high nibble of byte 1 specifies the bit instruction, as given in Table 5.26. Table 5.26. Bit Instructions Instruction 1 Bit Instr (dir8) Byte 0(x) A 9 xxxx Byte 1 0 bit Byte2 dir8 addr Byte 3 rel addr
Table 5.27. Byte 1 (High Nibble) for Bit Instructions xxxx 1 2 3 7 8 9 A B C D E F Bit Instruction JBC bit JB bit JNB bit ORL CY, bit ANL CY, bit MOV bit, CY MOV CY, bit CPL bit CLR bit SETB bit ORL CY, /bit ANL CY, /bit
Table 5.28. PUSH/POP Instructions Instruction PUSH #data PUSH #data16 PUSH Rm PUSH WRj PUSH DRk MOV DRk, PC POP Rm POP WRj POP DRk C C C C C C D D D Byte 0(x) A A A A A A A A A 0 0 m j/2 k/4 k/4 m j/2 k/4 Byte 1 2 6 8 9 B 1 8 9 B #data #data16 (high) #data16 (low) Byte 2 Byte 3
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Table 5.29. Control Instructions Instruction EJMP addr24 ECALL addr24 LJMP @WRj LCALL @WRj EJMP @DRk ECALL @DRk ERET JE rel JNE rel JLE rel JG rel JSL rel JSGE rel JSLE rel JSG rel TRAP 8 9 8 9 8 9 A 8 7 2 3 4 5 0 1 B Byte 0 A A 9 9 9 9 A 8 8 8 8 8 8 8 8 9 rel rel rel rel rel rel rel rel Byte 1 addr[23:16] addr[23:16] j/2 j/2 k/4 k/4 4 4 8 8 Byte 2 addr[15:8] addr[15:8] Byte 3 addr[7:0] addr[7:0]
Table 5.30. Displacement/Extended MOVs Instructions Instruction MOV Rm, @WRj +dis16 MOVWRk, @WRj +dis16 MOV Rm, @DRk +dis24 MOV WRj, @DRk +dis24 MOV @WRj +dis16, Rm MOV @WRj +dis16, WRk MOV @DRk +dis24, Rm MOV @DRk +dis24, WRj MOVS WRj, Rm MOVZ WRj, RM MOV WRj, @WRj MOV WRj, @DRk MOV @WRj, WRj MOV @DRk, WRj MOV dir8, Rm MOV dir8, WRj MOV dir8, DRk 5.22 0 4 2 6 1 5 3 7 1 0 0 0 1 1 7 7 7 Byte 0 9 9 9 9 9 9 9 9 A A B B B B A A A m j/2 m j/2 m j/2 m j/2 j/2 j/2 j/2 k/4 j/2 k/4 m j/2 k/4 Byte 1 j/2 k2 k/4 k/4 j/2 k2 k/4 k/4 m m 8 A 8 A 1 5 D j/2 j/2 j/2 j/2 dir8 addr dir8 addr dir8 addr Rev. C - May 7, 1999 0 0 0 0 Byte 2 dis[15:8] dis[15:8] dis[15:8] dis[15:8] dis[15:8] dis[15:8] dis[15:8] dis[15:8] Byte 3 dis[7:0] dis[7:0] dis[7:0] dis[7:0] dis[7:0] dis[7:0] dis[7:0] dis[7:0]
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Instruction MOV dir16, Rm MOV dir16, WRj MOV dir16, DRk MOV @WRj, Rm MOV @DRk, Rm 7 7 7 7 7 Byte 0 A A A A A m j/2 k/4 j/2 k/4 Byte 1 1 7 F 9 B Byte 2 dir16 addr (high) dir16 addr (high) dir16 addr (high) m m 0 0 Byte 3 dir16 addr (low) dir16 addr (low) dir16 addr (low)
Table 5.31. INC/DEC Instructions Instruction 1 2 3 4 5 6 INC Rm, #short INC WRj, #short INC DRk, #short DEC Rm, #short DEC WRj, #short DEC DRk, #short 0 0 0 1 1 1 Byte 0(x) B B B B B B m j/2 k/4 m j/2 k/4 Byte 1 00 01 11 00 01 11 vv vv vv vv vv vv
Table 5.32. Encoding for INC/DEC Instructions vv 00 01 10 #short 1 2 4
Table 5.33. Shifts Instructions Instruction 1 2 3 4 5 6 SRA Rm SRA WRj SRL Rm SRl WRj SLL Rm SLL WRj 0 0 1 1 3 3 Byte 0(x) E E E E E E m j/2 m j/2 m j/2 Byte 1 0 4 0 4 0 4
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5.3. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its length in bytes, and its execution time in states. Notes: D The instruction execution times given in the tables are for code executing from on-chip code memory and for data that is read from and written to on-chip RAM. Execution times are increased by executing code from external memory, accessing peripheral SFRs, accessing data in external memory, using wait states, or extending the ALE pulse. D For some instructions, accessing the Port SFRs, Px, x = 0-3, increases the execution time. These cases are noted individually in the tables.
5.3.1. Execution Times for Instructions that Access the Ports SFRs
The execution times for some instructions increases when the instruction accesses a Port SFR (Px, with x = 0-3) as opposed to any other SFR. Table 5.34. lists these instructions and the execution times for Case 0 : D Case 0: Code executes from on-chip ROM/OTPROM/EPROM and accesses locations in on-chip data RAM. The Port SFRs are not accessed. In cases 1 to 4, the instructions access a Port SFR : D Case 1: Code executes from on-chip ROM/OTPROM/EPROM and accesses a Port SFR. D Case 2: Code executes from external memory with no wait state and a short ALE (not extended) and accesses a Port SFR. D Case 3: Code executes from external memory with one wait state and a short ALE (not extended) and accesses a Port SFR. D Case 4: Code executes from external memory with one wait state and an extended ALE, and accesses a Port SFR. The times for Cases 1 through 4 are expressed as the number of state times to add to the state times given for Case 0.
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Table 5.34. State Times to Access the Port SFRs Case 0 Execution Times Binary ADD A, dir8 ADD Rm, dir8 ADDC A, dir8 ANL A, dir8 ANL CY, bit ANL CY, bit51 ANL CY, /bit ANL CY, /bit51 ANL dir8, #data ANL dir8, A ANL Rm, dir8 CLR bit CLR bit51 CMP Rm, dir8 CPL bit CPL bit51 DEC dir8 INC dir8 MOV A, dir8 MOV bit, CY MOV bit51, CY MOV CY, bit MOV CY, bit51 MOV dir8, #data MOV dir8, A MOV dir8, Rm MOV dir8, Rn MOV Rm, dir8 MOV Rn, dir8 ORL A, dir8 ORL CY, bit Rev. C - May 7, 1999 1 3 1 1 3 1 3 1 3 2 3 4 2 3 4 2 2 2 1 4 2 3 1 3 2 4 2 3 1 1 3 Source 1 2 1 1 2 1 2 1 3 2 2 3 2 2 3 2 2 2 1 3 2 2 1 3 2 3 3 2 2 1 2 Case 1 1 1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 2 2 1 2 2 1 1 1 1 1 1 1 1 1 1 Additional State Times Case 2 2 2 2 2 2 2 2 2 4 4 2 4 4 2 4 4 4 4 2 4 4 2 2 2 2 2 2 2 2 2 2 Case 3 3 3 3 3 3 3 3 3 6 6 3 6 6 3 6 6 6 6 3 6 6 3 3 3 3 3 3 3 3 3 3 Case 4 4 4 4 4 4 4 4 4 8 8 4 8 8 4 8 8 8 8 4 8 8 4 4 4 4 4 4 4 4 4 4 5.25
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Instruction ORL CY, bit51 ORL CY, /bit ORL CY, /bit51 ORL dir8, #data ORL dir8, A ORL Rm, dir8 SETB bit SETB bit51 SUB Rm, dir8 SUBB A, dir8 XCh A, dir8 XRL A, dir8 XRL dir8, #data XRL dir8, A XRL Rm, dir8 Case 0 Execution Times Binary 1 3 1 3 2 3 4 2 3 1 3 1 3 2 3 Source 1 2 1 3 2 2 3 2 2 1 3 1 3 2 2 Case 1 1 1 1 1 2 1 2 2 1 1 2 1 2 2 1 Additional State Times Case 2 2 2 2 2 4 2 4 4 2 2 4 2 4 4 2 Case 3 3 3 3 3 6 3 6 6 3 3 6 3 6 6 3 Case 4 4 4 4 4 8 4 8 8 4 4 8 4 8 8 4
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Table 5.35. Summary of Add and Subtract Instructions Add Subtract Add with Carry Subtract with Borrow Mnemonic , A, Rn ADD A, dir8 A, @Ri A, #data Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 ADD SUB Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk A, Rn ADDC SUBB A, dir8 A, @Ri A, #data Note :
1. 2. A shaded cell denotes an instruction in the C51 Architecture. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
ADD , SUB , ADDC , SUBB , Notes Reg to acc Direct byte to acc Indirect addr to acc Immediate data to acc Byte reg to/from byte reg Word reg to/from word reg Dword reg to/from dword reg Immediate 8-bit data to/from byte reg
dest opnd dest opnd + src opnd dest opnd dest opnd - src opnd (A) (A) + src opnd + carry bit (A) (A) - src opnd - carry bit Binary Mode Bytes 1 2 1 2 3 3 3 4 5 5 4 4 5 5 4 4 1 2 1 2 States 1 1 (2) 2 1 2 3 5 3 4 6 3 (2) 4 3 4 3 4 1 1 (2) 2 1 Source Mode Bytes 2 2 2 2 2 2 2 3 4 4 2 3 4 4 3 3 2 2 2 2 States 2 1 (2) 3 1 1 2 4 2 3 5 2 (2) 3 2 3 2 3 2 1 (2) 3 1
Immediate 16-bit data to/from word reg 16-bit unsigned immediate data to/from dword reg Direct addr to/from byte reg Direct addr to/from word reg Direct addr (64K) to/from byte reg Direct addr (64K) to/from word reg Indirect addr (64K) to/from byte reg Indirect addr (16M) to/from byte reg Reg to/from acc with carry Direct byte to/from acc with carry Indirect RAM to/from acc with carry Immediate data to/from acc with carry
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Table 5.36. Summary of Compare Instructions Compare Mnemonic , Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 CMP DRk, #1data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk Reg with reg Word reg with word reg Dword reg with dword reg Reg with immediate data Word reg with immediate 16-bit data Dword reg with immediate data Dword reg with immediate data zero-extended one-extended 16-bit 16-bit CMP , Notes dest opnd - src opnd Binary Mode Bytes 3 3 3 4 5 5 5 4 4 5 5 4 4 States 2 3 5 3 4 6 6 3 (1) 4 3 4 3 4 Source Mode Bytes 2 2 2 3 4 4 4 2 3 4 4 3 3 States 1 2 4 2 3 5 5 2 (1) 3 2 3 2 3
Direct addr from byte reg Direct addr from word reg Direct addr (64K) from byte reg Direct addr (64K) from word reg Indirect addr (64K) from byte reg Indirect addr (16M) from byte reg
Note : 1. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
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Table 5.37. Summary of Increment and Decrement Instructions Increment Increment Increment Decrement Decrement Mnemonic , A Rn INC DEC A, dir8 A, @Ri Rm, #short ADD SUB INC Notes :
1. 2. A shaded cell denotes an instruction in the C51 Architecture. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
INC DPTR INC byte INC , DEC byte DEC , Notes acc Reg Direct byte Indirect RAM Byte reg by 1, 2, or 4 Word reg by 1, 2, or 4 Double word reg by 1, 2, or 4 Data pointer
(DPTR) (DPTR) + 1 byte byte + 1 dest opnd dest opnd + src opnd byte byte - 1 dest opnd dest opnd - src opnd Binary Mode Bytes 1 1 2 1 3 3 3 1 2 States 1 1
(2)
Source Mode Bytes 1 2 2 2 2 2 2 1 States 1 2 2 (2) 4 1 1 3 1
3 2 2 4 1
WRj, #short DRk, #short DPTR
Table 5.38. Summary of Multiply, Divide and Decimal-adjust Instructions Multiply Divide Decimal-adjust ACC for Addition (BCD) Mnemonic , AB MUL Rmd, Rms WRjd, WRjs AB DIV DA Note :
1. 2. A shaded cell denotes an instruction in the C51 Architecture. If this instruction addresses an I/O Port (Px, x = 3:0), add 1 to the number of states.
MUL MUL AB DIV , DIV AB DA A
(2) (B:A) = A x B (2) (A) = Quotient; (B) = Remainder (2) Binary Mode Source Mode Bytes 1 2 2 1 2 2 1 States 5 5 11 10 10 20 1
Notes Multiply A and B Multiply byte reg and byte reg Multiply word reg and word reg Divide A and B Divide byte reg and byte reg Divide word reg and word reg Decimal adjust acc
Bytes 1 3 3 1 3 3 1
States 5 6 12 10 11 21 1
Rmd, Rms WRjd, WRjs A
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Table 5.39. Summary of Logical Instructions Logical AND Logical OR Logical Exclusive OR Clear Complement Rotate Mnemonic , A, Rn A, dir8 A, @Ri A, #data dir8, A dir8, #data Rmd, Rms WRjd, WRjs Rm, #data ANL ORL XRL WRj, #data16 DRk, #0data16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk CLR CPL RL RLC RR RRC A A A A A A Reg to acc Direct byte to acc Indirect addr to acc Immediate data to acc Acc to direct byte Immediate data to direct byte Byte reg to/from byte reg Word reg to/from word reg Immediate 8-bit data to/from byte reg Immediate 16-bit data to/from word reg 16-bit unsigned immediate data to/from dword reg Direct addr to/from byte reg Direct addr to/from word reg Direct addr (64K) to/from byte reg Direct addr (64K) to/from word reg Indirect addr (64K) to/from byte reg Indirect addr (16M) to/from byte reg Clear acc Complement acc Rotate acc left Rotate acc left through the carry Rotate acc right Rotate acc right through the carry ANL , ORL , XRL , CLR A CPL A RXX A Notes dest opnd dest opnd src opnd dest opnd dest opnd V src opnd dest opnd dest opnd src opnd (A) 0 (Ai) (Ai) Binary Mode Bytes 1 2 1 2 2 3 3 3 4 5 5 4 4 5 5 4 4 1 1 1 1 1 1 2 States 1 1 (2) 2 1
(4)
Source Mode Bytes 2 2 2 2 2 3 2 2 3 4 4 3 3 4 4 3 3 1 1 1 1 1 1 States 2 1 (2) 3 1 2 (4) 3 (4) 1 2 2 3 5 2 (2) 3 2 3 2 3 1 1 1 1 1 1
3 (4) 2 3 3 4 6 3 (2) 4 3 4 3 4 1 1 1 1 1 1
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Table 5.40. Summary of Logical Instructions (Cont'd) Shift SWAP Mnemonic SLL , Rm WRj Rm SRA WRj Rm WRj A SXX Rm or Wj A Notes Shift byte reg left through the MSB Shift word reg left through the MSB Shift byte reg right Shift word reg right Shift byte reg left Shift word reg left Swap nibbles within the acc A3:0 A7:4 Binary Mode Bytes 3 3 3 3 3 3 1 States 2 2 2 2 2 2 2 Source Mode Bytes 2 2 2 2 2 2 1 States 1 1 1 1 1 1 2
SRL SWAP Note :
1. 2. 3.
A shaded cell denotes an instruction in the C51 Architecture. If this instruction addresses an I/O Port (Px, x = 3:0), add 1 to the number of states. If this instruction addresses an I/O Port (Px, x = 3:0), add 2 to the number of states.
Table 5.41. Summary of Move Instructions Move (2) Move with Sign Extension Move with Zero Extension Move Code Byte Move to external Mem Move from external Mem Mnemonic , A, Rn A, dir8 A, @Ri A, #data Rn, A MOV Rn, dir8 Rn, #data dir8, A dir8, Rn dir8, dir8 dir8, @Ri dir8, #data @Ri, A @Ri, dir8 Rev. C - May 7, 1999 Reg to acc Direct byte to acc Indirect RAM to acc Immediate data to acc Acc to reg Direct byte to reg Immediate data to reg Acc to direct byte Reg to direct byte Dir byte to direct byte Indir RAM to direct byte Immediate data to direct byte Acc to indirect RAM Dir byte to indirect RAM MOV , MOVS , MOVZ , MOVC , MOVX , MOVX , Notes destination src opnd destination src opnd with sign extend destination src opnd with zero extend A code byte external mem (A) A source opnd in external mem Binary Mode Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 1 States 1 1 (3) 2 1 1
(3)
Source Mode Bytes 2 2 2 2 2 3 3 2 3 3 3 3 2 3 States 2 1 (3) 3 1 2 2 (3) 2 2 (3) 3 (3) 3 4 3 (3) 4 4 5.31
1
(3)
2 (3) 3 3 3 (3) 3 3
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Binary Mode Mnemonic , @Ri, #data DPTR, #data16 Rmd, Rms WRjd, WRjs DRkd, DRks Rm, #data WRj, #data16 DRk, #0data16 DRk, #1data16 DRk, dir8 DRk, dir16 Rm, dir8 WRj, dir8 Rm, dir16 WRj, dir16 Rm, @WRj Rm, @DRk WRjd, @WRjs WRj, @DRk dir8, Rm MOV dir8, WRj dir16, Rm dir16, WRj @WRj, Rm @DRk, Rm @WRjd, WRjs @DRk, WRj dir8, DRk dir16, DRk Rm, @WRj +dis16 Rm, @DRk +dis24 @WRj +dis16, Rm @DRk +dis24, Rm Notes Imeediate data to indirect RAM Load Data Pointer with a 16-bit const Byte reg to byte reg Word reg to word reg Dword reg to dword reg Immediate 8-bit data to byte reg Immediate 16-bit data to word reg zero-ext 16bit immediate data to dword reg one-ext 16bit immediate data to dword reg Direct addr to dword reg Direct addr (64K) to dword reg Direct addr to byte reg Direct addr to word reg Direct addr (64K) to byte reg Direct addr (64K) to word reg Indirect addr (64K) to byte reg Indirect addr (16M) to byte reg Indirect addr (64K) to word reg Indirect addr (16M) to word reg Byte reg to direct addr Word reg to direct addr Byte reg to direct addr (64K) Word reg to direct addr (64K) Byte reg to indirect addr (64K) Byte reg to indirect addr (16M) Word reg to indirect addr (64K) Word reg to indirect addr (16M) Dword reg to direct addr Dword reg to direct addr (64K) Indirect addr with disp (64K) to byte reg Indirect addr with disp (16M) to byte reg Byte reg to indirect addr with disp (64K) Byte reg to indirect addr with disp (16M) Bytes 2 3 3 3 3 4 5 5 5 4 4 4 4 5 5 4 4 4 4 4 4 5 5 4 4 4 4 4 5 5 5 5 5 5 5 5 5 4 3 States 3 2 2 2 3 3 3 5 5 6 6
(3)
Source Mode Bytes 3 3 2 2 2 3 4 4 4 3 4 3 3 4 4 3 3 3 3 3 3 4 4 3 3 3 3 3 4 4 4 4 4 4 4 4 4 States 4 2 1 1 2 2 2 4 4 5 5 2 (3) 3 2 3 2 3 3 4 3 (3) 4 3 4 3 4 4 5 6 6 5 6 6 7 5 6 6 7
4 3 4 2 4 4 5
(3)
5 4 5 4 5 5 6 7 7 6 7 7 8 6 7 7 8
WRj, @WRj +dis16 Indirect addr with disp (64K) to word reg WRj, @WRj +dis24 Indirect addr with disp (16M) to word reg @WRj +dis16, WRj Word reg to indirect addr with disp (64K) @DRk +dis24, WRj Word reg to indirect addr with disp (16M) 5.32
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Binary Mode Mnemonic MOVH MOVS MOVZ MOVC , DRk(hi), #data16 WRj, Rm WRj, Rm A, @A +DPTR A, @A +PC A, @Ri MOVX A, @DPTR @Ri, A @DPTR, A Note :
1. 2. 3. 4. A shaded cell denotes an instruction in the C51 Architecture. Instructions that move bits are in Table 5.43. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states. External memory addressed by instructions in the C51 Architecture is in the region specified by DPXL (reset value = 01h).
Source Mode Bytes 4 2 2 1 1 2 1 1 1 States 2 1 1 6 6 5 5 4 5
Notes 16-bit immediate data into upper word of dword reg Byte reg to word reg with sign extension Byte reg to word reg with zeros extension Code byte relative to DPTR to acc Code byte relative to PC to acc External mem (8-bit addr) to acc (4) External mem (16-bit addr) to acc (4) Acc to external mem (8-bit addr) (4) Acc to external mem (16-bit addr) (4)
Bytes 5 3 3 1 1 1 1 1 1
States 3 2 2 6 6 4 5 4 5
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Table 5.42. Summary of Exchange, Push and Pop Instructions Exchange Contents Exchange Digit Push Pop Mnemonic , A, Rn XCH XCHD A, dir8 A, @Ri A, @Ri dir8 #data #data16 PUSH Rm WRj DRk Dir POP Rm WRj DRk Note :
1. 2. A shaded cell denotes an instruction in the C51 Architecture. If this instruction addresses an I/O Port (Px, x = 0-3), add 1 to the number of states.
XCh , XCHD , PUSH POP Notes Acc and reg Acc and direct addr Acc and on-chip RAM (8-bit addr)
A $ src opnd A3:0 $ on-chip RAM bits 3:0 SP SP +1; (SP) src dest (SP); SP SP -1 Binary Mode Bytes 1 2 1 1 2 4 5 3 3 3 2 3 3 3 States 3 3 (2) 4 4 2 4 5 4 6 10 3/3 3 5 9 Source Mode Bytes 2 2 2 2 2 3 4 2 2 2 2 2 2 2 States 4 3 (2) 5 5 2 3 5 3 5 9 3/3 2 4 8
Acc and low nibble in on-chip RAM (8-bit addr) Push direct byte onto stack Push immediate data onto stack Push 16-bit immediate data onto stack Push byte reg onto stack Push word reg onto stack Push double word reg onto stack Pop direct byte from stack Pop byte reg from stack Pop word reg from stack Pop double word reg from stack
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Table 5.43. Summary of Bit Instructions Clear Bit Set Bit Complement Bit AND Carry with Bit AND Carry with Complement of Bit OR Carry with Bit ORL Carry with Complement of Bit Move Bit to Carry Move Bit from Carry Mnemonic , CY CLR bit51 bit CY SETB bit51 bit CY CPL bit51 bit CY, bit51 ANL CY, bit CY, bit51 ANL/ CY, /bit CY, bit51 ORL CY, bit CY, bit51 ORL/ CY, /bit CY, bit51 CY, bit MOV bit51, CY bit, CY Note :
1. 2. 3. A shaded cell denotes an instruction in the C51 Architecture. If this instruction addresses an I/O Port (Px, x = 3:0), add 1 to the number of states. If this instruction addresses an I/O Port (Px, x = 3:0), add 2 to the number of states.
CLR bit SETB bit CPL bit ANL CY, bit ANL CY, /bit ANL CY, bit ANL CY, /bit MOV CY, bit MOV bit, CY Notes
bit 0 bit 1 bit bit CY CY bit CY CY bit CY CY V bit CY CY V bit CY bit bit CY Binary Mode Bytes 1 2 4 1 2 4 1 2 4 2 4 2 4 2 4 2 4 2 4 2 4 States 1 2 (2) 4 1 2 (2) 4 (2) 1 2 (2) 4 (2) 1 (3) 3 (3) 1 (3) 3 (3) 1 (3) 3 (3) 1 (3) 3 (3) 1 (3) 3 (3) 2 (2) 4 (2) Source Mode Bytes 1 2 3 1 2 3 1 2 3 2 3 2 3 2 3 2 3 2 3 2 3 States 1 2 (2) 3 1 2 (2) 3 (2) 1 2 (2) 3 (2) 1 (3) 2 (3) 1 (3) 2 (3) 1 (3) 2 (3) 1 (3) 2 (3) 1 (3) 2 (3) 2 (2) 3 (2)
Clear carry Clear direct bit Clear direct bit Set carry Set direct bit Set direct bit Complement carry Complement direct bit Complement direct bit And direct bit to carry And direct bit to carry And complemented direct bit to carry And complemented direct bit to carry Or direct bit to carry Or direct bit to carry Or complemented direct bit to carry Or complemented direct bit to carry Move direct bit to carry Move direct bit to carry Move carry to direct bit Move carry to direct bit
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5.4. Instruction Descriptions
This section describes each instruction in the C251 Architecture. Table 5.44. defines the symbols (-, n,1, 0, ?) used to indicate the effect of the instruction on the flags in the PSW and PSW1 registers. For a conditional jump instruction, "!" indicates that a flag influences the decision to jump. Table 5.44. Flag Symbols Symbol - n 1 0 ? ! The instruction does not modify the flag. The instruction sets or clears the flag, as appropriate. The instruction sets the flag. The instruction clears the flag. The instruction leaves the flag in an indeterminate state. For a conditional jump instruction: the state of the flag before the instruction executes influences the decision to jump or not jump. Description
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ACALL Function:
Absolute call
Description:
Unconditionally calls a subroutine at the specified address. The instruction increments the 3-byte PC twice to obtain the address of the following instruction, then pushes bytes 0 and 1 of the result onto the stack (byte 0 first) and increments the stack pointer twice. The destination address is obtained by successively concatenating bits 15-11 of the incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called must therefore start within the same 2-Kbyte "page" of the program memory as the first byte of the instruction following ACALL.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The stack pointer (SP) contains 07h and the label "SUBRTN" is at program memory location 0345h. After executing the instruction ACALL SUBRTN at location 0123h, SP contains 09h; on-chip RAM locations 09h and 08h contain 01h and 25h, respectively; and the PC contains 0345h.
[Encoding]
a10 | a9 | a8 | 1 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 1 addr7-addr4 addr3-addr0 Operation: ACALL (PC) (PC) + 2 (SP) (SP) + 1 ((SP)) (PC.7:0) (SP) (SP) + 1 ((SP)) (PC.15:8) (PC.10:0) page address
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ADD , Function:
Add
Description:
Adds the source operand to the destination operand, which can be a register or the accumulator, leaving the result in the register or accumulator. If there is a carry out of bit 7 (CY), the CY flag is set. If byte variables are added, and if there is a carry out of bit 3 (AC), the AC flag is set. For addition of unsigned integers, the CY flag indicates that an overflow occurred. If there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6, the OV flag is set. When adding signed integers, the OV flag indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Bit 6 and bit 7 in this description refer to the most significant byte of the operand (8, 16 or 32 bit) Four source operand addressing modes are allowed: register, direct, register-indirect and immediate.
FLAGS :
CY n AC n OV n N n Z n
Example:
Register 1 contains 0C3h (11000011B) and register 0 contains 0AAh (10101010B). After executing the instruction ADD R1,R0 register 1 contains 6Dh (01101101B), the AC flag is clear, and the CY and OV flags are set.
ADD A,#data
[Encoding]
24 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] immed. data Operation: ADD (A) (A) + #data
ADD A,dir8
K
If this instruction addresses a Port (Px, x = 0-3), add 1 state.
[Encoding]
25 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 5.38 addr7-addr0 Operation: ADD (A) (A) + (dir8) Rev. C - May 7, 1999
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ADD A,@Ri
[Encoding]
2 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: ADD (A) (A) + ((Ri))
ADD A,Rn
[Encoding]
2 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1 rrr Operation: ADD (A) (A) + (Rn)
ADD Rmd,Rms
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] C ssss SSSS Operation: ADD (Rmd) (Rmd) + (Rms)
ADD WRjd, WRjs
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] D tttt TTTT Operation: ADD (WRjd) (WRjd) + (WRjs)
ADD DRkd,DRks
[Encoding]
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2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] F uuuu UUUU Operation: ADD (DRkd) (DRkd) + (DRks)
ADD Rm,#data
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E ssss 0 Operation: ADD (Rm) (Rm) + #data immed data
ADD WRj,#data16
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 4 immed data hi Operation: ADD (WRj) (WRj) + #data16 immed data low
ADD DRk,#0data16
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E uuuu 8 immed data hi immed data low
Operation: ADD (DRk) (DRk) + #data16
ADD Rm,dir8
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 5.40 E ssss 1 addr7-addr4 Operation: ADD (Rm) (Rm) + (dir8) Rev. C - May 7, 1999 addr3-addr0
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ADD WRj,dir8
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 5 addr7-addr4 Operation: ADD (WRj) (WRj) + (dir8) addr3-addr0
ADD Rm,dir16
[Encoding]
2 E ssss 3 addr15- addr12 addr11-addr8 addr7-addr4 addr3-addr0
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]
Operation: ADD (Rm) (Rm) + (dir16)
ADD WRj,dir16
[Encoding]
2 E tttt 7 addr15- addr12 addr11-addr8 addr7-addr4 addr3-addr0
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]
Operation: ADD (WRj) (WRj) + (dir16)
ADD Rm,@WRj
[Encoding]
2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 9 ssss Operation: ADD (Rm) (Rm) + ((WRj)) 0
ADD Rm,@DRk
[Encoding]
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2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E uuuu B ssss Operation: ADD (Rm) (Rm) + ((DRk)) 0
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ADDC A, Function:
Add with carry
Description:
Simultaneously adds the specified byte variable, the CY flag and the accumulator contents, leaving the result in the accumulator. If there is a carry out of bit 7 (CY), the CY flag is set; if there is a carry out of bit 3 (AC), the AC flag is set. When adding unsigned integers, the CY flag indicates that an overflow occurred. If there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6, the OV flag is set. When adding signed integers, the OV flag indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Bit 6 and bit 7 in this description refer to the most significant byte of the operand (8, 16 or 32 bit) Four source operand addressing modes are allowed: register, direct, register-indirect and immediate.
FLAGS :
CY n AC n OV n N n Z n
Example :
The accumulator contains 0C3h (11000011B), register 0 contains 0AAh (10101010B) and the CY flag is set. After executing the instruction ADDC A,R0 the accumulator contains 6Eh (01101110B), the AC flag is clear and the CY and OV flags are set.
ADDC A,#data
[Encoding]
34 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] immed. data Operation: ADDC (A) (A) + (CY) + #data
ADDC A,dir8
[Encoding]
35 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 addr7-addr0 Operation: ADDC (A) (A) + (CY) + (dir8) 5.43
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ADDC A,@Ri
[Encoding]
3 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: ADDC (A) (A) + (CY) + ((Ri))
ADDC A,Rn
[Encoding]
3 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr Operation: ADDC (A) (A) + (CY) + (Rn)
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AJMP addr11 Function:
Absolute jump
Description:
Transfers program execution to the specified address, which is formed at run time by concatenating the upper five bits of the PC (after incrementing the PC twice), opcode bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2-Kbyte "page" of program memory as the first byte of the instruction following AJMP.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The label "JMPADR" is at program memory location 0123h. After executing the instruction AJMP JMPADR at location 0345h the PC contains 0123h.
[Encoding]
a10 | a9 | a8 | 0 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 1 addr7-addr4 addr3-addr0 Operation: AJMP (PC) (PC) + 2 (PC.10:0) page address
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ANL , Function:
Logical-AND
Description:
Performs the bitwise logical-AND () operation between the specified variables and stores the results in the destination variable. The two operands allow 10 addressing mode combinations. When the destination is the register or accumulator, the source can use register, direct, register-indirect or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. Note :
When this instruction is used to modify an output Port, the value used as the original Port data is read from the output data latch, not the input pins.
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
Register 1 contains 0C3h (11000011B) and register 0 contains 55h (01010101B). After executing the instruction ANL R1, R0 register 1 contains 41h (01000001B). When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be an immediate constant contained in the instruction or a value computed in the register or accumulator at run time. The instruction ANL P1,#01110011B clears bits 7, 3, and 2 of output Port 1.
ANL dir8,A
[Encoding]
52 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] addr7-addr0 Operation: ANL (dir8) (dir8) (A)
ANL dir8,#data
[Encoding]
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Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ANL (dir8) (dir8) #data
ANL A,#data
[Encoding]
54 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] immed data Operation: ANL (A) (A ) #data
ANL A,dir8
[Encoding]
55 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] addr7-addr0 Operation: ANL (A) (A ) (dir8)
ANL A,@Ri
[Encoding]
5 Hex Code in: Binary Mode = [Encoding] Source Mode =[A5][Encoding] 011i Operation: ANL (A) (A ) ((Ri))
ANL A,Rn
[Encoding]
5 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Rev. C - May 7, 1999 1rrr Operation: ANL (A) (A ) (Rn) 5.47
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ANL Rmd,Rms
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] C ssss SSSS Operation: ANL (Rmd) (Rmd) (Rms)
ANL WRjd,WRjs
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] D tttt TTTT Operation: ANL (WRjd) (WRjd) (WRjs)
ANL Rm,#data
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] F ssss 0 Operation: ANL (Rm) (Rm) #data immed data
ANL WRj,#data16
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 4 immed data hi Operation: ANL (WRj) (WRj) #data16 immed data low
ANL Rm,dir8
[Encoding]
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5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E ssss 1 Operation: ANL (Rm) (Rm) (dir8) addr7-addr4 addr3-addr0
ANL WRj,dir8
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 5 Operation: ANL (WRj) (WRj) (dir8) addr7-addr4 addr3-addr0
ANL Rm,dir16
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E ssss 3 Operation: ANL (Rm) (Rm) (dir16) addr15-addr8 addr7-addr0
ANL WRj,dir16
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] eE tttt 7 Operation: ANL (WRj) (WRj) (dir16) addr15-addr8 addr7-addr0
ANL Rm,@WRj
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 E tttt 9 Operation: ANL (Rm) (Rm) ((WRj)) 5.49 ssss 0
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ANL Rm,@DRk
[Encoding]
5 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E uuuu B Operation: ANL (Rm) (Rm) ((DRk)) ssss 0
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ANL CY, Function:
Logical-AND for bit variables
Description:
If the boolean value of the source bit is a logical 0, clear the CY flag; otherwise leave the CY flag in its current state. A slash ("/") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. Only direct addressing is allowed for the source operand.
FLAGS :
CY n AC _ OV _ N _ Z _
Example :
Set the CY flag if, and only if, P1.0 = 1, ACC. 7 = 1 and OV = 0: MOV CY,P1.0 ; Load carry with input pin state ANL CY,ACC.7 ; AND carry with accumulator bit 7 ANL CY,/OV ; AND with inverse of overflow flag
ANL CY,bit51
[Encoding]
8 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 2 bit addr Operation: ANL (CY) (CY) (bit51)
ANL CY,/bit51
[Encoding]
B Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 0 bit addr Operation: ANL (CY) (CY) (bit51) 5.51
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ANL CY,bit
[Encoding]
A Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 9 8 0yyy Operation: ANL (CY) (CY) (bit) bit addr
ANL CY,/bit
[Encoding]
A Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 9 F 0yyy Operation: ANL (CY) (CY) (bit) bit addr
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CJNE ,,rel Function:
Compare and jump if not equal.
Description:
Compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. If the unsigned integer value of is less than the unsigned integer value of , the CY flag is set. Neither operand is affected. The first two operands allow four addressing mode combinations: the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant.
FLAGS :
CY 3 AC _ OV _ N 3 Z 3
Example :
The accumulator contains 34h and R7 contains 56h. After executing the first instruction in the sequence CJNE R7,#60h,NOT_EQ ;R7 = 60h ; . . . ... NOT_EQ: JC REQ_LOW ; IF R7 < 60h ;R7 > 60h ;... ... the CY flag is set and program execution continues at label NOT_EQ. By testing the CY flag, this instruction determines whether R7 is greater or less than 60h. If the data being presented to Port 1 is also 34h, then executing the instruction, WAIT: CJNE A,P1,WAIT clears the CY flag and continues with the next instruction in the sequence, since the accumulator does equal the data read from Port 1. (If some other value was being input on Port 1, the program loops at this point until the Port 1 data changes to 34h.)
CJNE A,#data,rel
[Encoding]
B4 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] immed data rel addr Operation: (PC) (PC) + 3 IF [(A) #data] THEN (PC) (PC) + relative offset IF [(A) < #data] THEN (CY) 1 ELSE (CY) 0 5.53
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CJNE A,dir8,rel
[Encoding]
B5 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] addr7-addr0 rel addr Operation: (PC) (PC) + 3 IF [(A) (dir8)] THEN (PC) (PC) + relative offset IF [(A) < (dir8)] THEN (CY) 1 ELSE (CY) 0
CJNE @Ri,#data,rel
[Encoding]
B Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i immed data rel addr Operation: (PC) (PC) + 3 IF [((Ri)) #data] THEN (PC) (PC) + relative offset IF [((Ri)) < #data] THEN (CY) 1 ELSE (CY) 0
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CJNE Rn,#data,rel
[Encoding]
B Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr immed data rel addr Operation: (PC) (PC) + 3 IF [(Rn) #data] THEN (PC) (PC) + relative offset IF [(Rn) < #data] THEN (CY) 1 ELSE (CY) 0
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CLR A Function:
Clear accumulator
Description:
Clears the accumulator (i.e., resets all bits to zero).
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
The accumulator contains 5Ch (01011100B). The instruction CLR A clears the accumulator to 00h (00000000B).
[Encoding]
E Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 4 Operation: CLR (A) 0
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CLR bit Function:
Clear bit
Description:
Clears the specified bit. CLR can operate on the CY flag or any directly addressable bit.
FLAGS : Only for instructions with CY as the operand.
CY n AC _ OV _ N _ Z _
Example :
Port 1 contains 5Dh (01011101B). After executing the instruction CLR P1.2 Port 1 contains 59h (01011001B).
CLR bit51
[Encoding]
C2 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] bit addr Operation: CLR (bit51) 0
CLR CY
[Encoding]
C3 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: CLR (CY) 0
Rev. C - May 7, 1999
5.57
TSC80251
CLR bit
K
If this instruction addresses a Port (Px, x = 0-3), add 2 states.
[Encoding]
A Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 9 C 0 yyy Operation: CLR (bit) 0 bit addr
5.58
Rev. C - May 7, 1999
TSC80251
CMP , Function:
Compare
Description:
Subtracts the source operand from the destination operand. The result is not stored in the destination operand. If a borrow is needed for bit 7, the CY (borrow) flag is set; otherwise it is clear. When subtracting signed integers, the OV flag indicates a negative result when a negative value is subtracted from a positive value, or a positive result when a positive value is subtracted from a negative value. Bit 7 in this description refers to the most significant byte of the operand (8, 16 or 32 bit) The source operand allows four addressing modes: register, direct, immediate and indirect.
FLAGS :
CY n AC n OV n N n Z n
Example :
Register 1 contains 0C9h (11001001B) and register 0 contains 54h (01010100B). The instruction CMP R1,R0 clears the CY and AC flags and sets the OV flag.
CMP Rmd,Rms
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] C ssss SSSS Operation: CMP (Rmd) - (Rms)
CMP WRjd,WRjs
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 E tttt TTTT Operation: CMP (WRjd) - (WRjs) 5.59
TSC80251
CMP DRkd,DRks
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] F uuuu UUUU Operation: CMP (DRkd) - (DRks)
CMP Rm,#data
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E ssss 0 Operation: CMP (Rm) - #data immed data
CMP WRj,#data16
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 4 Operation: CMP (WRj) - #data16 immed data hi immed data low
CMP DRk, #0data16
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E uuuu 8 Operation: CMP (DRk) - #0data16 immed data hi immed data hi
CMP DRk,#1data16
[Encoding]
5.60 Rev. C - May 7, 1999
TSC80251
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E uuuu C Operation: CMP (DRk) - #1data16 immed data hi immed data hi
CMP Rm,dir8
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E ssss 1 Operation: CMP (Rm) - (dir8) addr7-addr0
CMP WRj,dir8
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 5 Operation: CMP (WRj) - (dir8) addr7-addr0
CMP Rm,dir16
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E ssss 3 Operation: CMP (Rm) - (dir8) addr15-addr8 addr7-addr0
CMP WRj,dir16
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 E tttt 7 Operation: CMP (WRj) - (dir16) 5.61 addr15-addr8 addr7-addr0
TSC80251
CMP Rm,@WRj
[Encoding]
B Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] E tttt 9 Operation: CMP (Rm) - ((WRj)) ssss 0000
CMP Rm,@DRk
[Encoding]
1011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1011 Operation: CMP (Rm) - ((DRk)) ssss 0000
5.62
Rev. C - May 7, 1999
TSC80251
CPL A Function:
Complement accumulator
Description:
Logically complements () each bit of the accumulator (one's complement). Clear bits which are set and set bits which are cleared.
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
The accumulator contains 5Ch (01011100B). After executing the instruction CPL A the accumulator contains 0A3h (10100011B).
[Encoding]
F4 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: CPL (A) (A)
Rev. C - May 7, 1999
5.63
TSC80251
CPL bit Function:
Complement bit
Description:
Complements () the specified bit variable. A clear bit is set, and a set bit is cleared. CPL can operate on the CY or any directly addressable bit. Note:
When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin.
FLAGS : Only for instructions with CY as the operand.
CY n AC _ OV _ N _ Z _
Example :
Port 1 contains 5Bh (01011101B). After executing the instruction sequence CPL P1.1 CPL P1.2 Port 1 contains 5Bh (01011011B).
CPL bit51
[Encoding]
B2 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] bit addr Operation: CPL (bit51) (bit51)
CPL CY
[Encoding]
B3 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: CPL (CY) (CY)
CPL bit
[Encoding]
5.64 Rev. C - May 7, 1999
TSC80251
A Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 9 B 0yyy Operation: CPL (bit) (bit) bit addr
Rev. C - May 7, 1999
5.65
TSC80251
DA A Function:
Decimal-adjust accumulator for addition
Description:
Adjusts the 8-bit value in the accumulator that resulted from the earlier addition of two variables (each in packed-BCD format), producing two 4-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If accumulator bits 3:0 are greater than nine (XXXX1010-XXXX1111), or if the AC flag is set, six is added to the accumulator, producing the proper BCD digit in the low nibble. This internal addition sets the CY flag if a carry out of the lowest 4 bits propagated through all higher bits, but it does not clear the CY flag otherwise. If the CY flag is now set or if the upper four bits now exceed nine (1010XXXX-1111XXXX), these four bits are incremented by six, producing the proper BCD digit in the high nibble. Again, this sets the CY flag if there was a carry out of the upper four bits, but does not clear the carry. The CY flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple-precision decimal addition. The OV flag is not affected. All of this occurs during one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00h, 06h, 60h or 66h to the accumulator, depending on initial accumulator and PSW conditions. Note :
DA A cannot simply convert a Hexadecimal number in the accumulator to BCD notation, nor does DA A apply to decimal subtraction.
FLAGS :
CY n AC _ OV _ N 3 Z 3
Example :
The accumulator contains 56h (01010110B), which represents the packed BCD digits of the decimal number 56. Register 3 contains 67h (01100111B), which represents the packed BCD digits of the decimal number 67. The CY flag is set. After executing the instruction sequence ADDC A,R3. DA A the accumulator contains 0BEh (10111110B) and the CY and AC flags are clear. The Decimal Adjust instruction then alters the accumulator to the value 24h (00100100B), indicating the packed BCD digits of the decimal number 24, the lower two digits of the decimal sum of 56, 67, and the carry-in. The CY flag is set by the Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum of 56, 67 and 1 is 124. BCD variables can be incremented or decremented by adding 01h or 99h. If the accumulator contains 30h (representing the digits of 30 decimal), then the instruction sequence: ADD A, #99h. DA A leaves the CY flag set and 29h in the accumulator, since 30 + 99 = 129. The low byte of the sum can be interpreted to mean 30 - 1 = 29. [Encoding] 1101 5.66 0100 Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: DA (Contents of accumulator are BCD) IF [[(A.3:0) > 9] V [(AC) = 1]] THEN (A.3:0) (A.3:0) + 6 AND IF [[(A.7:4) > 9] V [(CY) = 1]] THEN (A.7:4) (A.7:4) + 6
Rev. C - May 7, 1999
5.67
TSC80251
DEC byte Function:
Decrement
Description:
Decrements the specified byte variable by 1. An original value of 00h underflows to 0FFh. Four operands addressing modes are allowed: accumulator, register, direct or register-indirect. Note :
When this instruction is used to modify an output Port, the value used as the original Port data is read from the output data latch, not the input pins.
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
Register 0 contains 7Fh (01111111B). On-chip RAM locations 7Eh and 7Fh contain 00h and 40h, respectively. After executing the instruction sequence: DEC @R0 DEC R0 DEC @R0 register 0 contains 7Eh and on-chip RAM locations 7Eh and 7Fh are set to 0FFh and 3Fh, respectively.
DEC A
[Encoding] 0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 Operation: DEC (A) (A) - 1
DEC dir8
[Encoding] 0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 5.68 0101 addr7-addr0 Operation: DEC (dir8) (dir8) - 1 Rev. C - May 7, 1999
TSC80251
DEC @Ri
[Encoding] 0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: DEC ((Ri)) ((Ri)) - 1
DEC Rn
[Encoding] 0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr Operation: DEC (Rn) (Rn) - 1
Rev. C - May 7, 1999
5.69
TSC80251
DEC , Function:
Decrement
Description:
Decrements the specified variable at the destination operand by 1, 2 or 4. An original value of 00h underflows to 0FFh.
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
Register 0 contains 7Fh (01111111B). After executing the instruction sequence DEC R0,#1 register 0 contains 7Eh.
DEC Rm,#short
[Encoding] 0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1011 ssss 01vv Operation: DEC (Rm) (Rm) - #short
DEC WRj,#short
[Encoding] 0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1011 tttt 01vv Operation: DEC (WRj) (WRj) - #short
DEC DRk,#short
[Encoding] 0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 5.70 1011 uuuu 11vv Operation: DEC (DRk) (DRk) - #short Rev. C - May 7, 1999
TSC80251
DIV , Function:
Divide
Description:
Divides the unsigned integer in the register by the unsigned integer operand in register addressing mode and clears the CY and OV flags. For byte operands (, = Rmd,Rms) the result is 16 bits. The 8-bit quotient is stored in the higher byte of the word where Rmd resides; the 8-bit remainder is stored in the lower byte of the word where Rmd resides. For example: register 1 contains 251 (0FBh or 11111011B) and register 5 contains 18 (12h or 00010010B). After executing the instruction DIV R1,R5 register 0 contains 13 (0Dh or 00001101B); register 1 contains 17 (11h or 00010001B), since 251 = (13 x 18) + 17; and the CY and OV bits are clear (See Flags).
FLAGS : The CY flag is cleared. The N flag is set if the MSB of the quotient is set. The Z flag is set if the quotient is zero.:
CY 0 AC n OV n N n Z n
Exception: if contains 00h, the values returned in both operands are undefined; the CY flag is cleared, OV flag is set, and the rest of the flags are undefined.
FLAGS :
CY 0 AC ? OV 1 N ? Z ?
DIV Rmd,Rms
[Encoding] 1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1100 ssss SSSS Operation: DIV (8-bit operands) (Rmd) remainder (Rmd) / (Rms) if md = 0,2,4,..,14 (Rmd+1) quotient (Rmd) / (Rms) (Rmd-1) remainder (Rmd) / (Rms) if md = 1,3,5,..,15 (Rmd) quotient (Rmd) / (Rms)
DIV WRjd,WRjs
[Encoding] Rev. C - May 7, 1999 5.71
TSC80251
1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1101 tttt TTTT Operation: DIV (16-bit operands) (WRjd) remainder (WRjd) / (WRjs) if jd = 0, 4, 8, ... 28 (WRjd+2) quotient (WRjd) / (WRjs) (WRjd-2) remainder (WRjd) / (WRjs)) if jd = 2, 6, 10, ... 30 (WRjd) quotient (WRjd) / (WRjs
For example, for a destination register WR4, assume the quotient is 1122h and the remainder is 3344h. Then, the results are stored in these register file locations: Location Contents 4 33h 5 44h 6 11h 7 22h
5.72
Rev. C - May 7, 1999
TSC80251
DIV AB Function:
Divide
Description:
Divides the unsigned 8-bit integer in the accumulator by the unsigned 8-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The CY and OV flags are cleared. Exception: if register B contains 00h, the values returned in the accumulator and register B are undefined; the CY flag is cleared and the OV flag is set.
FLAGS :
CY 0 For division by zero: AC n OV n N n Z n
FLAGS :
CY 0 AC ? OV 1 N ? Z ?
Example :
The accumulator contains 251 (0FBh or 11111011B) and register B contains 18 (12h or 00010010B). After executing the instruction DIV AB the accumulator contains 13 (0Dh or 00001101B); register B contains 17 (11h or 00010001B), since 251 = (13 x 18) + 17; and the CY and OV flags are clear. [Encoding] 1000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 Operation: DIV (A) quotient (A)/(B) (B) remainder (A)/(B)
Rev. C - May 7, 1999
5.73
TSC80251
DJNZ , Function:
Decrement and jump if not zero
Description:
Decrements the specified location by 1 and branches to the address specified by the second operand if the resulting value is not zero. An original value of 00h underflows to 0FFh. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note :
When this instruction is used to modify an output Port, the value used as the original Port data is read from the output data latch, not the input pins.
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
The on-chip RAM locations 40h, 50h, and 60h contain 01h, 70h, and 15h, respectively. After executing the following instruction sequence: DJNZ 40h,LABEL1 DJNZ 50h,LABEL2 DJNZ 60h,LABEL on-chip RAM locations 40h, 50h, and 60h contain 00h, 6Fh, and 15h, respectively, and program execution continues at label LABEL2. (The first jump was not taken because the result was zero.) This instruction provides a simple way of executing a program loop a given number of times, or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The instruction sequence, TOGGLE : MOV R2, #8 CPL P1.7 DJNZ R2, TOGGLE toggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse lasts three states: two for DJNZ and one to alter the pin.
DJNZ dir8,rel
[Encoding] 1101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0101 addr7-addr0 rel addr Operation: DJNZ (PC) (PC) + 2 (dir8) (dir8) - 1 IF [[(dir8) > 0] or [(dir8) < 0]] THEN (PC) (PC) + rel Rev. C - May 7, 1999
5.74
TSC80251
DJNZ Rn,rel
[Encoding] 1101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 1rrr rel addr Operation: DJNZ (PC) (PC) + 2 (Rn) (Rn) - 1 IF [[(Rn) > 0] or [(Rn) < 0]] THEN (PC) (PC) + rel
Rev. C - May 7, 1999
5.75
TSC80251
ECALL Function:
Extended call
Description:
Calls a subroutine located at the specified address. The instruction adds four to the program counter to generate the address of the next instruction and then PUSHes the 24-bit result onto the stack (high byte first), incrementing the stack pointer by three. The 8 bits of the high word and the 16 bits of the low word of the PC are then loaded, respectively, with the second, third and fourth bytes of the ECALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the full 16-Mbyte memory space.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The stack pointer contains 07h and the label "SUBRTN" is assigned to program memory location 123456h. After executing the instruction ECALL SUBRTN at location 054321h, SP contains 0Ah; on-chip RAM locations 08h, 09h and 0Ah contain 05h, 43h and 21h, respectively; and the PC contains 123456h.
ECALL addr24
[Encoding] 1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 addr23- addr16 addr15-addr8 Operation: ECALL (PC) (PC) + 4 (SP) (SP) + 1 ((SP)) (PC.23:16) (SP) (SP) + 1 ((SP)) (PC.15:8) (SP) (SP) + 1 ((SP)) (PC.7:0) (PC) (addr.23:0) addr7-addr0
ECALL @DRk
[Encoding] 1001 5.76 1001 uuuu Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ECALL (PC) (PC) + 4 (SP) (SP) + 1 ((SP)) (PC.23:16) (SP) (SP) + 1 ((SP)) (PC.15:8) (SP) (SP) + 1 ((SP)) (PC.7:0) (PC) ((DRk))
Rev. C - May 7, 1999
5.77
TSC80251
EJMP Function:
Extended jump
Description:
Causes an unconditional branch to the specified address by loading the 8 bits of the high order and 16 bits of the low order words of the PC with the second, third, and fourth instruction bytes. The destination may be therefore be anywhere in the full 16-Mbyte memory space.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The label "JMPADR" is assigned to the instruction at program memory location 123456h. The instruction is EJMP JMPADR
EJMP addr24
[Encoding] 1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 addr23- addr16 addr15-addr8 Operation: EJMP (PC) (addr.23:0) addr7-addr0
EJMP @DRk
[Encoding] 1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 uuuu Operation: EJMP (PC) ((DRk))
5.78
Rev. C - May 7, 1999
TSC80251
ERET Function:
Extended return
Description:
POPs byte 2, byte 1, and byte 0 of the 3-byte PC successively from the stack and decrements the stack pointer by 3. Program execution continues at the resulting address, which normally is the instruction immediately following ECALL.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The stack pointer contains 0Bh. On-chip RAM locations 08h, 09h and 0Ah contain 01h, 23h and 49h, respectively. After executing the instruction ERET the stack pointer contains 08h and program execution continues at location 012349h. [Encoding] 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 Operation: ERET (PC.7:0) ((SP)) (SP) (SP) - 1 (PC.15:8) ((SP)) (SP) (SP) - 1 (PC.23:16) ((SP)) (SP) (SP) - 1
Rev. C - May 7, 1999
5.79
TSC80251
INC Function:
Increment
Description:
Increments the specified byte variable by 1. An original value of 0FFh overflows to 00h. Three addressing modes are allowed for 8-bit operands: register, direct, or register-indirect. Note :
When this instruction is used to modify an output Port, the value used as the original Port data is read from the output data latch, not the input pins.
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
Register 0 contains 7Eh (011111110B) and on-chip RAM locations 7Eh and 7Fh contain 0FFh and 40h, respectively. After executing the instruction sequence: INC @R0 INC R0 INC @R0 register 0 contains 7Fh and on-chip RAM locations 7Eh and 7Fh contain 00h and 41h, respectively.
INC A
[Encoding] 0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 Operation: INC (A) (A) + 1
INC dir8
[Encoding] 0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 5.80 0101 addr7-addr0 Operation: INC (dir8) (dir8) + 1 Rev. C - May 7, 1999
TSC80251
INC @Ri
[Encoding] 0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: INC ((Ri) ((Ri)) + 1
INC Rn
[Encoding] 0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr Operation: INC (Rn) (Rn) + 1
Rev. C - May 7, 1999
5.81
TSC80251
INC , Function:
Increment
Description:
Increments the specified variable by 1, 2 or 4. An original value of 0FFh overflows to 00h.
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
Register 0 contains 7Eh (011111110B). After executing the instruction INC R0,#1 register 0 contains 7Fh.
INC Rm,#short
[Encoding] 0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1011 ssss 00vv Operation: INC (Rm) (Rm) + #short
INC WRj,#short
[Encoding] 0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1011 tttt 01vv Operation: INC (WRj) (WRj) + #short
INC DRk,#short
[Encoding] 0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 5.82 1011 uuuu 11vv Operation: INC (DRk) (DRk) + #shortdata pointer Rev. C - May 7, 1999
TSC80251
INC DPTR Function:
Increment data pointer
Description:
Increments the 16-bit data pointer by one. A 16-bit increment (modulo 216 ) is performed; an overflow of the low byte of the data pointer (DPL) from 0FFh to 00h increments the high byte of the data pointer (DPH) by one. An overflow of the high byte (DPH) does not increment the high word of the extended data pointer (DPX = DR56).
FLAGS :
CY _ AC _ OV _ N n Z n
Example :
Registers DPH and DPL contain 12h and 0FEh, respectively. After the instruction sequence: INC DPTR INC DPTR INC DPTR DPH and DPL contain 13h and 01h, respectively. [Encoding] 1010 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: INC (DPTR) (DPTR) + 1
Rev. C - May 7, 1999
5.83
TSC80251
JB bit51,rel JB bit,rel Function:
Jump if bit set
Description:
If the specified bit is a one, jump to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
Input Port 1 contains 11001010B and the accumulator contains 56h (01010110B). After the instruction sequence: JB P1.2,LABEL1 JB ACC.2,LABEL2 program execution continues at label LABEL2.
5.84
Rev. C - May 7, 1999
TSC80251
Variations
JB bit51,rel
0010 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 bit addr rel addr Operation: JB (PC) (PC) + 3 IF (bit51) = 1 THEN (PC) (PC) + rel
JB bit,rel
[Encoding] 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 0010 0yyy bit addr Operation: JB (PC) (PC) + 3 IF [(bit) = 1] THEN (PC) (PC) + rel rel addr
Rev. C - May 7, 1999
5.85
TSC80251
JBC bit51,rel JBC bit,rel Function:
Jump if bit is set and clear bit.
Description:
If the specified bit is one, branch to the specified address; otherwise proceed with the next instruction. The bit is not cleared if it is already a zero. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. Note :
When this instruction is used to test an output pin, the value used as the original data is read from the output data latch, not the input pin.
FLAGS :
CY ! AC _ OV _ N _ Z _
Example :
The accumulator contains 56h (01010110B). After the instruction sequence: JBC ACC.3,LABEL1 JBC ACC.2,LABEL2 the accumulator contains 52h (01010010B) and program execution continues at label LABEL2.
JBC bit51,rel
[Encoding] 0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 bit addr rel addr Operation: JBC (PC) (PC) + 3 IF [(bit51) = 1] THEN (bit51) 0 (PC) (PC) + rel
JBC bit,rel
[Encoding] 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 0001 0yyy Operation: JBC (PC) (PC) + 3 IF [(bit51) = 1] THEN (bit51) 0 (PC) (PC) + rel Rev. C - May 7, 1999 bit addr rel addr
5.86
TSC80251
JC rel Function:
Jump if carry is set
Description:
If the CY flag is set, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY ! AC _ OV _ N _ Z _
Example :
The CY flag is clear. After the instruction sequence: JC CPL JC [Encoding] 0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 rel addr Operation: JC (PC) (PC) + 2 IF [(CY) = 1] THEN (PC) (PC) + rel LABEL1 CY LABEL 2
the CY flag is set and program execution continues at label LABEL2.
Rev. C - May 7, 1999
5.87
TSC80251
JE rel Function:
Jump if equal
Description:
If the Z flag is set, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV _ N _ Z !
Example :
The Z flag is set. After executing the instruction JE LABEL1 program execution continues at label LABEL1. [Encoding] 0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JE (PC) (PC) + 2 IF [(Z) = 1] THEN (PC) (PC) + rel
5.88
Rev. C - May 7, 1999
TSC80251
JG rel Function:
Jump if greater than
Description:
If the Z flag and the CY flag are both clear, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV _ N ! Z _
Example :
The instruction JG LABEL1 causes program execution to continue at label LABEL1 if the Z flag and the CY flag are both clear. [Encoding] 0011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JG (PC) (PC) + 2 IF [[(Z) = 0] AND [(CY) = 0]] THEN (PC) (PC) + rel
Rev. C - May 7, 1999
5.89
TSC80251
JLE rel Function:
Jump if less than or equal
Description:
If the Z flag or the CY flag is set, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV _ N ! Z !
Example :
The instruction JLE LABEL1 causes program execution to continue at LABEL1 if the Z flag or the CY flag is set. [Encoding] 0010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JLE (PC) (PC) + 2 IF [[(Z) = 1] OR [(CY) = 1]] THEN (PC) (PC) + rel
5.90
Rev. C - May 7, 1999
TSC80251
JMP @A+DPTR Function:
Jump indirect
Description:
Adds the 8-bit unsigned content of the accumulator with the 16-bit data pointer and load the resulting sum into the lower 16 bits of the program counter. This is the address for subsequent instruction fetches. The contents of the accumulator and the data pointer are not affected.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The accumulator contains an even number from 0 to 6. The following sequence of instructions branchs to one of four AJMP instructions in a jump table starting at JMP_TBL : MOV DPTR,#JMP_TBL JMP @A+DPTR AJMP LABEL0 AJMP LABEL1 AJMP LABEL2 AJMP LABEL3 If the accumulator contains 04h at the start this sequence, execution jumps to LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at every other address. [Encoding] 0111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: JMP (PC.15:0) (A) + (DPTR)
Rev. C - May 7, 1999
5.91
TSC80251
JNB bit51,rel JNB bit,rel Function:
Jump if bit not set
Description:
If the specified bit is clear, branch to the specified address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
Input Port 1 contains 11001010B and the accumulator contains 56h (01010110B). After executing the instruction sequence: JNB P1.3,LABEL1 JNB ACC.3,LABEL2 program execution continues at label LABEL2.
JNB bit51,rel
[Encoding] 0011 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 bit addr rel addr Operation: JNB (PC) (PC) + 3 IF [(bit51) = 0] THEN (PC) (PC) + rel
JNB bit,rel
[Encoding] 1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 0011 00yy Operation: JNB (PC) (PC) + 3 IF [(bit) = 0] THEN (PC) (PC) + rel Rev. C - May 7, 1999 bit addr rel addr
5.92
TSC80251
JNC rel
Function: Jump if carry not set
Description:
If the CY flag is clear, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The CY flag is not modified.
FLAGS :
CY ! AC _ OV _ N _ Z _
Example :
The CY flag is set. The instruction sequence: JNC CPL JNC [Encoding] 0101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 rel addr Operation: JNC (PC) (PC) + 2 IF [(CY) = 0] THEN (PC) (PC) + rel LABEL1 CY LABEL2
clears the CY flag and causes program execution to continue at label LABEL2.
Rev. C - May 7, 1999
5.93
TSC80251
JNE rel Function:
Jump if not equal
Description:
If the Z flag is clear, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV _ N _ Z !
Example :
The instruction JNE LABEL1 causes program execution to continue at LABEL1 if the Z flag is clear. [Encoding] 0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JNE (PC) (PC) + 2 IF [(Z) = 0] THEN (PC) (PC) + rel
5.94
Rev. C - May 7, 1999
TSC80251
JNZ rel Function:
Jump if accumulator not zero
Description:
If any bit of the accumulator is set, branch to the specified address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified.
FLAGS :
CY _ AC _ OV _ N _ Z !
Example :
The accumulator contains 00h. After executing the instruction sequence: JNZ INC JNZ [Encoding] 0111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 rel addr Operation: JNZ (PC) (PC) + 2 IF [(A) 0] THEN (PC) (PC) + rel LABEL1 A LABEL2
the accumulator contains 01h and program execution continues at label LABEL2.
Rev. C - May 7, 1999
5.95
TSC80251
JSG rel Function:
Jump if greater than (signed)
Description:
If the Z flag is clear and the N flag and the OV flag have the same value, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV ! N ! Z !
Example :
The instruction JSG LABEL1 causes program execution to continue at LABEL1 if the Z flag is clear and the N flag and the OV flag have the same value. [Encoding] 0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JSG (PC) (PC) + 2 IF [(Z) = 0] AND [(N) = (OV)] THEN (PC) (PC) + rel
5.96
Rev. C - May 7, 1999
TSC80251
JSGE rel Function:
Jump if greater than or equal (signed)
Description:
If the N flag and the OV flag have the same value, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV ! N ! Z !
Example :
The instruction JSGE LABEL1 causes program execution to continue at LABEL1 if the N flag and the OV flag have the same value. [Encoding] 0101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JSGE (PC) (PC) + 2 IF [(N) = (OV)] THEN (PC) (PC) + rel
Rev. C - May 7, 1999
5.97
TSC80251
JSL rel Function:
Jump if less than (signed)
Description:
If the N flag and the OV flag have different values, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV ! N ! Z !
Example :
The instruction JSL LABEL1 causes program execution to continue at LABEL1 if the N flag and the OV flag have different values. [Encoding] 0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JSL (PC) (PC) + 2 IF [(N) (OV)] THEN (PC) (PC) + rel
5.98
Rev. C - May 7, 1999
TSC80251
JSLE rel Function:
Jump if less than or equal (signed)
Description:
If the Z flag is set OR if the the N flag and the OV flag have different values, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
FLAGS :
CY _ AC _ OV ! N ! Z !
Example :
The instruction JSLE LABEL1 causes program execution to continue at LABEL1 if the Z flag is set OR if the the N flag and the OV flag have different values. [Encoding] 0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1000 rel addr Operation: JSLE (PC) (PC) + 2 IF [[(Z) = 1] OR [(N) (OV)]] THEN (PC) (PC) + rel
Rev. C - May 7, 1999
5.99
TSC80251
JZ rel Function:
Jump if accumulator zero
Description:
If all bits of the accumulator are clear (zero), branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice. The accumulator is not modified.
FLAGS :
CY _ AC _ OV _ N _ Z !
Example :
The accumulator contains 01h. After executing the instruction sequence: JZ LABEL1 DEC A JZ LABEL2 the accumulator contains 00h and program execution continues at label LABEL2. [Encoding] 0110 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 rel. addr Operation: JZ (PC) (PC) + 2 IF [(A) = 0] THEN (PC) (PC) + rel
5.100
Rev. C - May 7, 1999
TSC80251
LCALL Function:
Long call
Description:
Calls a subroutine located at the specified address. The instruction adds three to the program counter to generate the address of the next instruction and then PUSHes the 16-bit result onto the stack (low byte first). The stack pointer is incremented by two. The high and low bytes of the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the 64-Kbyte region of memory where the next instruction is located.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The stack pointer contains 07h and the label "SUBRTN" is assigned to program memory location 1234h. After executing the instruction LCALL SUBRTN at location 0123h, the stack pointer contains 09h, on-chip RAM locations 08h and 09h contain 01h and 26h and the PC contains 1234h.
LCALL addr16
[Encoding] 0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 addr15-addr8 addr7-addr0 Operation: LCALL (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC.7:0) (SP) (SP) + 1 ((SP)) (PC.15:8) (PC) (addr.15:0)
LCALL @WRj
[Encoding] 1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 tttt 0100 Operation: LCALL (PC) (PC) + 3 (SP) (SP) + 1 ((SP)) (PC.7:0) (SP) (SP) + 1 ((SP)) (PC.15:8) (PC) ((WRj)) 5.101
Rev. C - May 7, 1999
TSC80251
LJMP Function:
Long Jump
Description:
Causes an unconditional branch to the specified address, by loading the high and low bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the 64-Kbyte memory region where the next instruction is located.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
The label "JMPADR" is assigned to the instruction at program memory location 1234h. After executing the instruction LJMP JMPADR at location 0123h, the program counter contains 1234h.
LJMP addr16
[Encoding] 0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 addr15-addr8 addr7-addr0 Operation: LJMP (PC) (addr.15:0)
LJMP @WRj
[Encoding] 1000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 tttt 0100 Operation: LJMP (PC) ((WRj))
5.102
Rev. C - May 7, 1999
TSC80251
MOV , Function:
Move byte variable
Description:
Copies the byte variable specified by the second operand into the location specified by the first operand. The source byte is not affected. This is by far the most flexible operation. Twenty-four combinations of source and destination addressing modes are allowed.
FLAGS :
CY _ AC _ OV _ N _ Z _
Example :
On-chip RAM location 30h contains 40h, on-chip RAM location 40h contains 10h, and input Port 1 contains 11001010B (0CAh). After executing the instruction sequence: MOV MOV MOV MOV MOV MOV R0,#30h ;R0 < = 30h A,@R0 ;A < = 40h R1,A ;R1 < = 40h B,@R1 ;B < = 10h @R1,P1 ;RAM (40h) < = 0CAh P2,P1 ;P2 #0CAh
register 0 contains 30h, the accumulator and register 1 contain 40h, register B contains 10h and on-chip RAM location 40h and output Port 2 contain 0CAh (11001010B).
Rev. C - May 7, 1999
5.103
TSC80251
MOV A,#data
[Encoding]
0111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 immed data Operation: MOV (A) #data
MOV dir8,#data
[Encoding]
0111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0101 addr7-addr0 immed data Operation: MOV (dir8) #data
MOV @Ri,#data
[Encoding]
0111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 011i immed data Operation: MOV ((Ri)) #data
MOV Rn,#data
[Encoding]
0111 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr immed data Operation: MOV (Rn) #data
MOV dir8,dir8
[Encoding]
1000 5.104 0101 addr7-addr0 addr7-addr0 Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: MOV (dir8) (dir8)
MOV dir8,@Ri
[Encoding]
1000 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i addr7-addr0 Operation: MOV (dir8) ((Ri))
MOV dir8,Rn
[Encoding]
1000 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr addr7-addr0 Operation: MOV (dir8) (Rn)
MOV @Ri,dir8
[Encoding]
1010 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i addr7-addr0 Operation: MOV ((Ri)) (dir8)
MOV Rn,dir8
[Encoding]
1010 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Rev. C - May 7, 1999 1rrr addr7-addr0 Operation: MOV (Rn) (dir8) 5.105
TSC80251
MOV A,dir8
[Encoding]
1110 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0101 addr7-addr0 Operation: MOV (A) (dir8)
MOV A,@Ri
[Encoding]
1110 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: MOV (A) ((Ri))
MOV A,Rn
[Encoding]
1110 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr Operation: MOV (A) (Rn)
MOV dir8,A
[Encoding]
1111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0101 addr7-addr0 Operation: MOV (dir8) (A )
MOV @Ri,A
[Encoding]
1111 5.106 011i Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: MOV ((Ri)) (A)
MOV Rn,A
[Encoding]
1111 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 111r Operation: MOV (Rn) (A)
MOV Rmd,Rms
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1100 ssss SSSS Operation: MOV (Rmd) (Rms)
MOV WRjd,WRjs
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1101 tttt TTTT Operation: MOV (WRjd) (WRjs)
MOV DRkd,DRks
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 1111 uuuu UUUU Operation: MOV (DRkd) (DRks) 5.107
TSC80251
MOV Rm,#data
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0000 Operation: MOV (Rm) #data immed data
MOV WRj,#data16
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0100 Operation: MOV (WRj) #data16 immed data hi immed data low
MOV DRk,#0data16
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1000 Operation: MOV (DRk) #0data16 immed data hi immed data low
MOV DRk,#1data16
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1100 Operation: MOV (DRk) #1data16 immed data hi immed data low
MOV Rm,dir8
[Encoding]
0111 5.108 1110 ssss 0001 addr7-addr0 Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (Rm) (dir8)
MOV WRj,dir8
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0101 Operation: MOV (WRj) (dir8) addr7-addr0
MOV DRk,dir8
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1101 Operation: MOV (DRk) (dir8) addr7-addr0
MOV Rm,dir16
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0011 Operation: MOV (Rm) (dir16) addr15-addr8 addr7-addr0
MOV WRj, dir16
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 1110 tttt 0111 Operation: MOV (WRj (dir16) 5.109 addr15-addr8 addr7-addr0
TSC80251
MOV DRk,dir16
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1111 Operation: MOV (DRk) (dir16) addr15-addr8 addr7-addr0
MOV Rm,@WRj
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 1001 Operation: MOV (Rm) ((WRj)) ssss 0000
MOV Rm,@DRk
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1011 Operation: MOV (Rm) ((DRk)) ssss 0000
MOV WRjd,@WRjs
[Encoding]
0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1011 TTTT 1000 Operation: MOV (WRjd) ((WRjs)) tttt 0000
MOV WRj,@DRk
[Encoding]
0000 5.110 1011 uuuu 1010 tttt 0000 Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (WRj) ((DRk))
Rev. C - May 7, 1999
5.111
TSC80251
MOV dir8,Rm
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 ssss 0011 Operation: MOV (dir8) (Rm) addr7-addr0
MOV dir8,WRj
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 tttt 0101 Operation: MOV (dir8) (WRj) addr7-addr0
MOV dir8,DRk
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 uuuu 1101 Operation: MOV (dir8) (DRk) addr7-addr0
MOV dir16,Rm
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 ssss 0011 Operation: MOV (dir16) (Rm) addr15-addr8 addr7-addr0
MOV dir16,WRj
[Encoding]
0111 5.112 1010 tttt 0111 addr15-addr8 addr7-addr0 Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: MOV (dir16) (WRj)
MOV dir16,DRk
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 uuuu 1111 Operation: MOV (dir16) (DRk) addr15-addr8 addr7-addr0
MOV @WRj,Rm
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 tttt 1001 Operation: MOV ((WRj)) (Rm) ssss 0000
MOV @DRk,Rm
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 uuuu 1011 Operation: MOV ((DRk)) (Rm) ssss 0000
MOV @WRjd,WRjs
[Encoding]
0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 1011 tttt 1000 Operation: MOV ((WRjd)) (WRjs) 5.113 TTTT 0000
TSC80251
MOV @DRk,WRj
Binary Mode Bytes States 4 6 Source Mode 3 5
[Encoding]
0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1011 uuuu 1010 Operation: MOV ((DRk)) (WRj) tttt 0000
MOV Rm,@WRj + dis16
Binary Mode Bytes States 5 6 Source Mode 4 5
[Encoding]
0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 ssss tttt Operation: MOV (Rm) ((WRj) + dis16) dis hi dis low
MOV WRj,@WRj + dis16
Binary Mode Bytes States 5 7 Source Mode 4 6
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 5.114 1001 tttt TTTT Operation: MOV (WRj) ((WRj) + dis16) Rev. C - May 7, 1999 dis hi dis low
TSC80251
MOV Rm,@DRk + dis24
Binary Mode Bytes States 5 7 Source Mode 4 6
[Encoding]
0010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 ssss uuuu Operation: MOV (Rm) ((DRk) + dis24) dis hi dis low
MOV WRj,@DRk + dis24
Binary Mode Bytes States 5 8 Source Mode 4 7
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 tttt uuuu Operation: MOV (WRj) ((DRk) + dis24) dis hi dis low
MOV @WRj + dis16,Rm
Binary Mode Bytes States 5 6 Source Mode 4 5
[Encoding]
0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 1001 tttt ssss Operation: MOV ((WRj) + dis16) (Rm) 5.115 dis hi dis low
TSC80251
MOV @WRj + dis16,WRj
Binary Mode Bytes States 5 7 Source Mode 4 6
[Encoding]
0101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 tttt TTTT Operation: MOV ((WRj) + dis16) (WRj) dis hi dis low
MOV @DRk + dis24,Rm
Binary Mode Bytes States 5 7 Source Mode 4 6
[Encoding]
0011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 uuuu ssss Operation: MOV ((DRk) + dis24) (Rm) dis hi dis low
MOV @DRk + dis24,WRj
Binary Mode Bytes States 5 8 Source Mode 4 7
[Encoding]
0111 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 5.116 1001 uuuu tttt Operation: MOV ((DRk) + dis24) (WRj) Rev. C - May 7, 1999 dis hi dis low
TSC80251
MOV , Function
Move bit data
Description
Copies the boolean variable specified by the second operand into the location specified by the first operand. One of the operands must be the CY flag; the other may be any directly addressable bit. Does not affect any other register. FLAGS : CY
n
AC
_
OV
_
N
_
Z
_
Example :
The CY flag is set, input Port 3 contains 11001001B and output Port 1 contains 35h (00110101B). After executing the instruction sequence: MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY the CY flag is clear and Port 1 contains 39h (00111001B).
MOV bit51,CY
Binary Mode Bytes States 2 2K Source Mode 2 2K
[Encoding]
1001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 bit addr Operation: MOV (bit51) (CY)
MOV CY,bit51
Binary Mode Bytes States Rev. C - May 7, 1999 2 1K Source Mode 2 1K 5.117
TSC80251
[Encoding]
1010 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 bit addr Operation: MOV (CY) (bit51)
MOV bit,CY
Binary Mode Bytes States 4 4K Source Mode 3 3K
[Encoding]
1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 1001 0yyy Operation: MOV (bit) (CY) bit addr
MOV CY,bit
Binary Mode Bytes States 4 3K Source Mode 3 2K
[Encoding]
1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 1010 0yyy Operation: MOV (CY) (bit) bit addr
5.118
Rev. C - May 7, 1999
TSC80251
MOV DPTR,#data16 Function:
Load data pointer with a 16-bit constant
Description:
Loads the 16-bit data pointer (DPTR) with the specified 16-bit constant. The high byte of the constant is loaded into the high byte of the data pointer (DPH). The low byte of the constant is loaded into the low byte of the data pointer (DPL). FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
After executing the instruction MOV DPTR,#1234h DPTR contains 1234h (DPH contains 12h and DPL contains 34h).
[Encoding]
1001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 immed data hi immed data low Operation: MOV (DPTR) #data16
Rev. C - May 7, 1999
5.119
TSC80251
MOVC A,@A+ Function:
Move code byte
Description:
Loads the accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit accumulator contents and the contents of a 16-bit base register, which may be the 16 LSBs of the data pointer or PC. In the latter case, the PC is incremented to the address of the following instruction before being added with the accumulator; otherwise the base register is not altered. 16-bit addition is performed. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
The accumulator contains a number between 0 and 3. The following instruction sequence translates the value in the accumulator to one of four values defined by the DB (define byte) directive. RELPC: INC MOVC RET DB DB DB DB A A,@A+PC 66h 77h 88h 99h
If the subroutine is called with the accumulator equal to 01h, it returns with 77h in the accumulator. The INC A before the MOVC instruction is needed to "get around" the RET instruction above the table. If several bytes of code separated the MOVC from the table, the corresponding number would be added to the accumulator instead.
MOVC A,@A+PC
[Encoding]
1000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: MOVC (PC) (PC) + 1 (A) ((A) + (PC))
MOVC A,@A+DPTR
[Encoding]
1001 5.120 0011 Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: MOVC (A) ((A) + (DPTR))
Rev. C - May 7, 1999
5.121
TSC80251
MOVH DRk,#data16 Function:
Move immediate 16-bit data to the high word of a dword (double-word) register.
Description:
Moves 16-bit immediate data to the high word of a dword (32-bit) register. The low word of the dword register is unchanged. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
The dword register DRk contains 5566 7788h. After the instruction MOVH DRk,#1122h executes, DRk contains 1122 7788h.
[Encoding]
0111 Hex Code in: Binary Mode =[A5] [Encoding] Source Mode = [Encoding] 1010 uuuu 1100 Operation: MOVH (DRk).31-16 #data16 immed data hi immed data low
5.122
Rev. C - May 7, 1999
TSC80251
MOVS WRj,Rm Function:
Move 8-bit register to 16-bit register with sign extension
Description:
Moves the contents of an 8-bit register to the low byte of a 16-bit register. The high byte of the 16-bit register is filled with the sign extension, which is obtained from the MSB of the 8- bit source register. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
8-bit register Rm contains 055h (01010101B) and the 16-bit register WRj contains 0FFFFh (11111111 11111111B). The instruction MOVS WRj,Rm moves the contents of register Rm (01010101B) to register WRj (i.e., WRj contains 00000000 01010101B).
[Encoding]
0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 tttt ssss Operation: MOVS (WRj).7-0 (Rm).7-0 (WRj).15-8 MSB
Rev. C - May 7, 1999
5.123
TSC80251
MOVX , Function:
Move external
Description:
Transfers data between the accumulator and a byte in external data RAM. There are two types of instructions. One provides an 8-bit indirect address to external data RAM; the second provides a 16-bit indirect address to external data RAM. In the first type of MOVX instruction, the contents of R0 or R1 in the current register bank provides an 8-bit address on Port 0. 8 bits are sufficient for external I/O expansion decoding or for a relatively small RAM array. For larger arrays, any Port pins can be used to output higher address bits. These pins would be controlled by an output instruction preceding the MOVX. In the second type of MOVX instruction, the data pointer generates a 16-bit address. Port 2 outputs the upper 8 address bits (from DPH) while Port 0 outputs the lower 8 address bits (from DPL). For both types of moves in nonpage mode, the data is multiplexed with the lower address bits on Port 0. In page mode, the data is multiplexed with the contents of P2 on Port 2 (8-bit address) or with the upper address bits on Port 2 (16-bit address). It is possible in some situations to mix the two MOVX types. A large RAM array with its upper address lines driven by P2 can be addressed via the data pointer, or with code to output upper address bits to P2 followed by a MOVX instruction using R0 or R1. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
The TSC80251 Microcontroller is operating in nonpage mode. An external 256-byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/I/O/Timer) is connected to Port 0. Port 3 provides control lines for the external RAM. Ports 1 and 2 are used for normal I/O. R0 and R1 contain 12h and 34h. Location 34h of the external RAM contains 56h. After executing the instruction sequence: MOVX A,@R1 MOVX @R0,A the accumulator and external RAM location 12h contain 56h.
MOVX A,@DPTR
[Encoding]
1110 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 5.124 0000 Operation: MOVX (A) ((DPTR)) Rev. C - May 7, 1999
TSC80251
MOVX A,@Ri
[Encoding]
1110 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 001i Operation: MOVX (A) ((Ri))
MOVX @DPTR,A
[Encoding]
1111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: MOVX ((DPTR)) (A)
MOVX @Ri,A
[Encoding]
1111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 001i Operation: MOVX ((Ri)) (A)
Rev. C - May 7, 1999
5.125
TSC80251
MOVZ WRj,Rm Function:
Move 8-bit register to 16-bit register with zero extension
Description:
Moves the contents of an 8-bit register to the low byte of a 16-bit register. The upper byte of the 16-bit register is filled with zeros. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
8-bit register Rm contains 055h (01010101B) and 16-bit register WRj contains 0FFFFh (11111111 11111111B). The instruction MOVZ WRj,Rm moves the contents of register Rm (01010101B) to register WRj. At the end of the operation, WRj contains 00000000 01010101B.
[Encoding]
0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 tttt ssss Operation: MOV (WRj).7-0 (Rm).7-0 (WRj).15-8 0
5.126
Rev. C - May 7, 1999
TSC80251
MUL , Function:
Multiply
Description:
Multiplies the unsigned integer in the source register with the unsigned integer in the destination register. Only register addressing is allowed. For 8-bit operands, the result is 16 bits. The most significant byte of the result is stored in the low byte of the word where the destination register resides. The least significant byte is stored in the following byte register. The OV flag is set if the product is greater than 255 (0FFh); otherwise it is cleared. For 16-bit operands, the result is 32 bits. The most significant word is stored in the low word of the the dword where the destination register resides. The least significant word is stored in the following word register. In this operation, the OV flag is set if the product is greater than 0FFFFh, otherwise it is cleared. The CY flag is always cleared. The N flag is set when the MSB of the result is set. The Z flag is set when the result is zero. FLAGS : CY
0
AC
_
OV
n
N
n
Z
n
Example :
Register R1 contains 80 (50h or 10010000B) and register R0 contains 160 (0A0h or 10010000B). After executing the instruction MUL R1,R0 which gives the product 12800 (3200h), register R0 contains 32h (00110010B), register R1 contains 00h, the OV flag is set and the CY flag is clear.
MUL Rmd,Rms
[Encoding]
1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1100 ssss SSSS Operation: MUL (8-bit operands) if md = 0, 2, 4, .., 14 Rmd high byte of the Rmd x Rms Rmd+1 low byte of the Rmd x Rms if md = 1, 3, 5, .., 15 Rmd-1 high byte of the Rmd x Rms Rmd low byte of the Rmd x Rms
MUL WRjd,WRjs
[Encoding]
1010 Rev. C - May 7, 1999 1101 tttt TTTT 5.127
TSC80251
Hex Code in: Binary Mode =[A5][Encoding] Source Mode = [Encoding] Operation: MUL (16-bit operands) if jd = 0, 4, 8, .., 28 WRjd high word of the WRjd x WRjs WRjd+2 low word of the WRjd x WRjs if jd = 2, 6, 10, .., 30 WRjd-2 high word of the WRjd x WRjs WRjd low word of the WRjd x WRjs
5.128
Rev. C - May 7, 1999
TSC80251
MUL AB Function:
Multiply
Description:
Multiplies the unsigned 8-bit integers in the accumulator and register B. The low byte of the 16-bit product is left in the accumulator, and the high byte is left in register in B. If the product is greater than 255 (0FFh) the OV flag is set; otherwise it is clear. The CY flag is always clear. FLAGS : CY
0
AC
_
OV
n
N
n
Z
n
Example :
The accumulator contains 80 (50h) and register B contains 160 (0A0h). After executing the instruction MUL AB which gives the product 12800 (3200h), register B contains 32h (00110010B), the accumulator contains 00h, the OV flag is set and the CY flag is clear.
[Encoding]
1010 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 Operation: MUL (A) low byte of (A) X (B) (B) high byte of (A) X (B)
Rev. C - May 7, 1999
5.129
TSC80251
NOP Function:
No operation
Description:
Execution continues at the following instruction. Affects the PC register only. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
We assume we are executing an internal code and you want to produce a low-going output pulse on bit 7 of Port 2 that lasts exactly 11 states. A simple CLR-SETB sequence generates an eight-state pulse. (Each instruction requires four states to write to a Port SFR.) You can insert three additional states (if no interrupts are enabled) with the following instruction sequence : CLR P2.7 NOP NOP NOP SETB P2.7
[Encoding]
0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 Operation: NOP (PC) (PC) + 1
5.130
Rev. C - May 7, 1999
TSC80251
ORL Function:
Logical-OR for byte variables
Description:
Performs the bitwise logical-OR operation (V) between the specified variables, storing the results in the destination operand. The destination operand can be a register, an accumulator or direct address. The two operands allow twelve addressing mode combinations. When the destination is the accumulator, the source can be register, direct, register-indirect or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. When the destination is register the source can be register, immediate, direct and indirect addressing. Note:
When this instruction is used to modify an output Port, the value used as the original Port data is read from the output data latch, not the input pins.
FLAGS : CY
_
AC
_
OV
_
N
n
Z
n
Example :
The accumulator contains 0C3h (11000011B) and R0 contains 55h (01010101B). After executing the instruction, ORL A, R0 the accumulator contains 0D7h (11010111B). When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be a constant data value in the instruction or a variable computed in the accumulator at run time. After executing the instruction ORL P1, #00110010B sets bits 5, 4 and 1 of output Port 1.
ORL dir8,A
[Encoding]
0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 addr7-addr0 Operation: ORL (dir8) (dir8) V (A)
ORL dir8,#data
[Encoding]
0100 Rev. C - May 7, 1999 0011 addr7-addr0 immed data 5.131
TSC80251
Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ORL (dir8) (dir8) V #data
ORL A,#data
[Encoding]
0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 immed data Operation: ORL (A) (A) V #data
ORL A,dir8
[Encoding]
0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0101 addr7-addr0 Operation: ORL (A) (A) V (dir8)
ORL A,@Ri
[Encoding]
0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: ORL (A) (A) V ((Ri))
ORL A,Rn
[Encoding]
0100 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 5.132 1rrr Operation: ORL (A) (A) V (Rn) Rev. C - May 7, 1999
TSC80251
ORL Rmd,Rms
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1100 ssss SSSS Operation: ORL (Rmd) (Rmd) V (Rms)
ORL WRjd,WRjs
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1101 tttt TTTT Operation: ORL (WRjd)(WRjd) V (WRjs)
ORL Rm,#data
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0000 Operation: ORL (Rm) (Rm) V #data immed data
ORL WRj,#data16
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0100 Operation: ORL (WRj) (WRj) V #data16 immed data hi immed data low
ORL Rm,dir8
[Encoding]
0100 Rev. C - May 7, 1999 1110 ssss 0001 addr7-addr0 5.133
TSC80251
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ORL (Rm) (Rm) V (dir8)
ORL WRj,dir8
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0101 Operation: ORL (WRj) (WRj) V (dir8) addr7-addr0
ORL Rm,dir16
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0011 Operation: ORL (Rm) (Rm) V (dir16) addr15-addr8 addr7-addr0
ORL WRj,dir16
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0111 Operation: ORL (WRj) (WRj) V (dir16) addr15-addr8 addr7-addr0
ORL Rm,@WRj
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 5.134 1110 tttt 1001 Operation: ORL (Rm) (Rm) V ((WRj)) Rev. C - May 7, 1999 ssss 0000
TSC80251
ORL Rm,@DRk
[Encoding]
0100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1011 Operation: ORL (Rm) (Rm) V ((DRk)) ssss 0000
Rev. C - May 7, 1999
5.135
TSC80251
ORL CY, Function:
Logical-OR for bit variables
Description:
Sets the CY flag if the Boolean value is a logical 1; leaves the CY flag in its current state otherwise. A slash ("/") preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. FLAGS : CY
n
AC
_
OV
_
N
_
Z
_
Example :
Set the CY flag if and only if P1.0 = 1, ACC.7 = 1 or OV = 0. MOV CY,P1.0 ;Load carry with input pin P1.0 ORL CY,ACC.7 ;Or carry with the accumulator bit 7 ORL CY,/OV ;Or carry with the inverse of OV.
ORL CY,bit51
[Encoding]
0111 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 bit addr Operation: ORL (CY) (CY) V (bit51)
ORL CY,/bit51
K If this instruction addresses a Port (Px, x = 0-3), add 1 state.
[Encoding]
1010 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 5.136 0000 bit addr Operation: ORL (CY) (CY) V (bit51) Rev. C - May 7, 1999
TSC80251
ORL CY,bit
[Encoding]
1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 0111 0yyy Operation: ORL (CY) (CY) V (bit) bit addr
ORL CY,/bit
[Encoding]
1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 1110 0yyy Operation: ORL (CY) (CY) V 0 (bit) bit addr
Rev. C - May 7, 1999
5.137
TSC80251
POP Function:
Pop from stack.
Description:
Reads the contents of the on-chip RAM location addressed by the stack pointer, then decrements the stack pointer by one. The value read at the original RAM location is transferred to the newly addressed location, which can be 8-bit or 16-bit. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example :
The stack pointer contains 32h and on-chip RAM locations 30h through 32h contain 01h, 23h, and 20h, respectively. After executing the instruction sequence: POP DPH POP DPL the stack pointer contains 30h and the data pointer contains 0123h. After executing the instruction POP SP the stack pointer contains 20h. Note that in this special case the stack pointer was decremented to 2Fh before it was loaded with the value popped (20h).
POP dir8
[Encoding]
1101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 addr7-addr0 Operation: POP (dir8) ((SP) (SP) (SP) - 1
POP Rm
[Encoding]
1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 ssss 1000 Operation: POP (Rm) ((SP)) (SP) (SP) - 1 Rev. C - May 7, 1999
5.138
TSC80251
POP WRj
[Encoding]
1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 tttt 1001 Operation: POP (SP) (SP) - 1 (WRj) ((SP)) (SP) (SP) - 1
POP DRk
[Encoding]
1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 uuuu 1011 Operation: POP (SP) (SP) - 3 (DRk) ((SP)) (SP) (SP) - 1
Rev. C - May 7, 1999
5.139
TSC80251
PUSH Function:
PUSH onto stack
Description:
Increments the stack pointer by one. The contents of the specified variable are then copied into the on-chip RAM location addressed by the stack pointer. FLAGS : CY
_
AC
_
OV
_
N
_
Z
_
Example: On entering an interrupt routine, the stack pointer contains 09h and the data pointer contains 0123h. After executing the instruction sequence: PUSH DPL PUSH DPH the stack pointer contains 0Bh and on-chip RAM locations 0Ah and 0Bh contain 01h and 23h, respectively.
5.140
Rev. C - May 7, 1999
TSC80251
PUSH dir8
[Encoding]
1100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 addr7-addr0 Operation: PUSH (SP) (SP) + 1 ((SP)) (dir8)
PUSH #data
[Encoding]
1100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 0000 0010 Operation: PUSH (SP) (SP) + 1 ((SP)) #data immed data
Rev. C - May 7, 1999
5.141
TSC80251
PUSH #data16
[Encoding]
1100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 0000 0110 Operation: PUSH (SP) (SP) + 1 ((SP)) #data16 (SP) (SP) + 1 immed data hi immed data low
PUSH Rm
[Encoding]
1100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 ssss 1000 Operation: PUSH (SP) (SP) + 1 ((SP)) (Rm)
5.142
Rev. C - May 7, 1999
TSC80251
PUSH WRj
[Encoding]
1100 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 tttt 1001 Operation: PUSH (SP) (SP) + 1 ((SP)) (DRk) (SP) (SP) + 1
PUSH DRk
[Encoding]
1011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1010 uuuu 1101 Operation: PUSH (SP) (SP) + 1 ((SP)) (DRk) (SP) (SP) + 3
Rev. C - May 7, 1999
5.143
TSC80251
RET Function:
Return from subroutine
Description:
Pops the high and low bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, which normally is the instruction immediately following ACALL or LCALL. FLAGS : CY _ AC _ OV _ N _ Z _
Example :
The stack pointer contains 0Bh and on-chip RAM locations 0Ah and 0Bh contain 01h and 23h, respectively. After executing the instruction, RET the stack pointer contains 09h and program execution continues at location 0123h.
[Encoding]
0010 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 Operation: RET (PC).15:8 ((SP)) (SP) (SP) - 1 (PC).7:0 ((SP)) (SP) (SP) - 1
5.144
Rev. C - May 7, 1999
TSC80251
RETI Function:
Return from interrupt
Description:
This instruction pops two or four bytes from the stack, depending on the INTR bit in the CONFIG1 register . If INTR = 0, RETI pops the high and low bytes of the PC successively from the stack and uses them as the 16-bit return address in region FF:.The stack pointer is decremented by two. No other registers are affected, and neither PSW nor PSW1 is automatically restored to its pre-interrupt status. If INTR = 1, RETI pops four bytes from the stack: PSW1 and the three bytes of the PC. The three bytes of the PC are the return address, which can be anywhere in the 16-Mbyte memory space. The stack pointer is decremented by four. PSW1 is restored to its pre-interrupt status, but PSW is not restored to its pre-interrupt status. No other registers are affected. For either value of INTR, hardware restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. Program execution continues at the return address, which normally is the instruction immediately after the point at which the interrupt request was detected. If an interrupt of the same or lower priority is pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed. FLAGS : CY _ AC _ OV _ N _ Z _
Example :
INTR = 0. The stack pointer contains 0Bh. An interrupt was detected during the instruction ending at location 0122h. On-chip RAM locations 0Ah and 0Bh contain 01h and 23h, respectively. After executing the instruction, RETI the stack pointer contains 09h and program execution continues at location 0123h.
[Encoding]
0011 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 Operation: Operation for INTR = 0 : RETI (PC).15:8 ((SP)) (SP) (SP) - 1 (PC).7:0 ((SP)) (SP) (SP) - 1 Operation for INTR = 1 : RETI (PC).15:8 ((SP)) (SP) (SP) - 1 (PC).7:0 ((SP)) (SP) (SP) - 1 (PC).23:16 ((SP)) (SP) (SP) - 1 PSW1 ((SP)) (SP) (SP) - 1 5.145
Rev. C - May 7, 1999
TSC80251
RL A Function:
Rotate accumulator left
Description:
Rotates the 8 bits in the accumulator one bit to the left. Bit 7 is rotated into the bit 0 position. FLAGS : CY _ AC _ OV _ N n Z n
Example :
The accumulator contains 0C5h (11000101B). After executing the instruction, RL A the accumulator contains 8Bh (10001011B); the CY flag is unaffected.
[Encoding]
0010 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: RL (A).a+1 (A).a (A).0 (A).7
5.146
Rev. C - May 7, 1999
TSC80251
RLC A Function:
Rotate accumulator left through the carry flag
Description:
Rotates the 8 bits in the accumulator and the CY flag one bit to the left. Bit 7 moves into the CY flag position and the original state of the CY flag moves into bit 0 position.
Description:
FLAGS : CY n AC _ OV _ N n Z n
Example :
The accumulator contains 0C5h (11000101B) and the CY flag is clear. After executing the instruction RLC A the accumulator contains 8Ah (10001010B) and the CY flag is set.
[Encoding]
0011 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: RLC (A).a+1 (A).a (A).0 (CY) (CY) (A) .7
Rev. C - May 7, 1999
5.147
TSC80251
RR A Function:
Rotate accumulator right
Description:
Rotates the 8 bits in the accumulator one bit to the right. Bit 0 is moved into the bit 7 position. FLAGS : CY _ AC _ OV _ N n Z n
Example :
The accumulator contains 0C5h (11000101B). After executing the instruction, RR A the accumulator contains 0E2h (11100010B) and the CY flag is unaffected.
[Encoding]
0000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: RR (A).a (A).a+1 (A).7 (A) .0
5.148
Rev. C - May 7, 1999
TSC80251
RRC A Function:
Rotate accumulator right through carry flag
Description:
Rotates the 8 bits in the accumulator and the CY flag one bit to the right. Bit 0 moves into the CY flag position; the original value of the CY flag moves into the bit 7 position. FLAGS : CY _ AC _ OV _ N n Z n
Example :
The accumulator contains 0C5h (11000101B) and the CY flag is clear. After executing the instruction RRC A the accumulator contains 62h (01100010B) and the CY flag is set.
[Encoding]
0001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: RRC (A).a (A).a+1 (A).7 (CY) (CY) (A).0
Rev. C - May 7, 1999
5.149
TSC80251
SETB Function:
Set bit
Description:
Sets the specified bit to one. SETB can operate on the CY flag or any directly addressable bit. FLAGS : No CY n
flags are affected except the CY flag for instruction with CY as the operand.
AC _ OV _ N _ Z _
Example:
The CY flag is clear and output Port 1 contains 34h (00110100B). After executing the instruction sequence: SETB CY SETB P1.0 the CY flag is set and output Port 1 contains 35h (00110101B).
SETB bit51
[Encoding]
1101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 bit addr Operation: SETB (bit51) 1
SETB CY
[Encoding]
1101 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0011 Operation: SETB (CY) 1
5.150
Rev. C - May 7, 1999
TSC80251
SETB bit
[Encoding]
1010 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 1101 0yyy Operation: SETB (bit) 1 bit addr
Rev. C - May 7, 1999
5.151
TSC80251
SJMP rel Function:
Short jump
Description:
Program control branches unconditionally to the specified address. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it. FLAGS : CY _ AC _ OV _ N _ Z _
Example :
The label "RELADR" is assigned to an instruction at program memory location 0123h. The instruction SJMP RELADR assembles into location 0100h. After executing the instruction, the PC contains 0123h. Note :
In the above example, the instruction following SJMP is located at 102h. Therefore, the displacement byte of the instruction is the relative offset (0123h-0102h) = 21h. Put another way, an SJMP with a displacement of 0FEh would be a one-instruction infinite loop.
[Encoding]
1000 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0000 rel addr Operation: SJMP (PC) (PC) + 2 (PC) (PC) + rel
5.152
Rev. C - May 7, 1999
TSC80251
SLL Function:
Shift logical left by 1 bit
Description:
Shifts the specified variable to the left by 1 bit, replacing the LSB with zero. The bit shifted out (MSB) is stored in the CY bit. FLAGS : CY n AC _ OV _ N n Z n
Example :
Register 1 contains 0C5h (11000101B). After executing the instruction SLL R 1 register 1 contains 8Ah (10001010B) and CY = 1.
SLL Rm
[Encoding]
0011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0000 Operation: SLL (Rm).a+1 (Rm).a (Rm).0 0 CY (Rm).7
SLL WRj
[Encoding]
0011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0100 Operation: SLL (WRj).b+1 (WRj).b (WRj).0 0 CY (WRj).15 5.153
Rev. C - May 7, 1999
TSC80251
SRA Function:
Shift arithmetic right by 1 bit
Description:
Shifts the specified variable to the arithmetic right by 1 bit. The MSB is unchanged. The bit shifted out (LSB) is stored in the CY bit. FLAGS : CY n AC _ OV _ N n Z n
Example :
Register 1 contains 0C5h (11000101B). After executing the instruction SRA R 1 register 1 contains 0E2h (11100010B) and CY = 1.
SRA Rm
[Encoding]
0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0000 Operation: SRA (Rm).7 (Rm).7 (Rm).a (Rm).a + 1 CY (Rm).0
SRA WRj
[Encoding]
0000 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0100 Operation: SRA (WRj).15 (WRj).15 (WRj).b (WRj).b+1 CY (WRj).0 Rev. C - May 7, 1999
5.154
TSC80251
SRL Function:
Shift logical right by 1 bit
Description:
SRL shifts the specified variable to the right by 1 bit, replacing the MSB with a zero. The bit shifted out (LSB) is stored in the CY bit. FLAGS : CY n AC _ OV _ N n Z n
Example :
Register 1 contains 0C5h (11000101B). After executing the instruction SRL R 1 register 1 contains 62h (01100010B) and CY = 1.
SRL Rm
[Encoding]
1101 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 0010 ssss 0000 Operation: SRL (Rm).7 0 (Rm).a (Rm) a + 1 CY (Rm).0
SRL WRj
[Encoding]
0001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0100 Operation: SRL (WRj).15 0 (WRj).b (WRj).b+1 CY (WRj).0 5.155
Rev. C - May 7, 1999
TSC80251
SUB , Function:
Subtract
Description:
Subtracts the specified variable from the destination operand, leaving the result in the destination operand. SUB sets the CY (borrow) flag if a borrow is needed for bit 7. Otherwise, CY is clear. When subtracting signed integers, the OV flag indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number. Bit 7 in this description refers to the most significant byte of the operand (8, 16, or 32 bit) The source operand allows four addressing modes: immediate, indirect, register and direct. FLAGS : CY n AC nK OV n N n Z n
K For word and dword subtractions, AC is not affected.
Example :
Register 1 contains 0C9h (11001001B) and register 0 contains 54h (01010100B). After executing the instruction SUB R1,R0 register 1 contains 75h (01110101B), the CY and AC flags are clear, and the OV flag is set.
SUB Rmd,Rms
[Encoding]
1001 Hex Code in: Binary Mode =[A5][Encoding] Source Mode = [Encoding] 1100 ssss SSSS Operation: SUB (Rmd) (Rmd) - (Rms)
SUB WRjd,WRjs
[Encoding]
1001 Hex Code in: Binary Mode =[A5][Encoding] Source Mode = [Encoding] 5.156 1101 tttt TTTT Operation: SUB (WRjd) (WRjd) - (WRjs) Rev. C - May 7, 1999
TSC80251
SUB DRkd,DRks
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1111 uuuu UUUU Operation: SUB (DRkd) (DRkd) - (DRks)
SUB Rm,#data
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0000 Operation: SUB (Rm) (Rm) - #data immed data
SUB WRj,#data16
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0100 Operation: SUB (WRj) (WRj) - #data16 immed data hi immed data low
SUB DRk,#data16
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1000 Operation: SUB (DRk) (DRk) - #data16 immed data hi immed data low
SUB Rm,dir8
[Encoding]
1001 Rev. C - May 7, 1999 1110 ssss 0001 addr7-addr0 5.157
TSC80251
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: SUB (Rm) (Rm) - (dir8)
SUB WRj,dir8
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0101 Operation: SUB (WRj) (WRj) - (dir8) addr7-addr0
SUB Rm,dir16
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0011 Operation: SUB (Rm) (Rm) - (dir16) addr15-addr8 addr7-addr0
SUB WRj,dir16
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0111 Operation: SUB (WRj) (WRj) - (dir16) addr15-addr8 addr7-addr0
SUB Rm,@WRj
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 5.158 1110 tttt 1001 Operation: SUB (Rm) (Rm) - ((WRj)) Rev. C - May 7, 1999 ssss 0000
TSC80251
SUB Rm,@DRk
[Encoding]
1001 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 uuuu 1011 Operation: SUB (Rm) (Rm) - ((DRk)) ssss 0000
Rev. C - May 7, 1999
5.159
TSC80251
SUBB A, Function:
Subtract with borrow
Description:
SUBB subtracts the specified variable and the CY flag together from the accumulator, leaving the result in the accumulator. SUBB sets the CY (borrow) flag if a borrow is needed for bit 7 and clears CY otherwise. (If CY was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the CY flag is subtracted from the accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers the OV flag indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number. Bit 6 and bit 7 in this description refer to the most significant byte of the operand (8, 16 or 32 bit) The source operand allows four addressing modes: register, direct, register-indirect or immediate. FLAGS : CY n AC n OV n N n Z n
Example :
The accumulator contains 0C9h (11001001B), register 2 contains 54h (01010100B), and the CY flag is set. After executing the instruction SUBB A,R2 the accumulator contains 74h (01110100B), the CY and AC flags are clear, and the OV flag is set.Notice that 0C9h minus 54h is 75h. The difference between this and the above result is due to the CY (borrow) flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by a CLR CY instruction.
SUBB A,#data
[Encoding]
1001 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 immed data Operation: SUBB (A) (A) - (CY) - #data
SUBB A,dir8
[Encoding]
1001 5.160 0101 addr7-addr0 Rev. C - May 7, 1999
TSC80251
Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: SUBB (A) (A) - (CY) - (dir8)
SUBB A,@Ri
[Encoding]
1001 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: SUBB (A) (A) - (CY) - ((Ri))
SUBB A,Rn
[Encoding]
1001 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr Operation: SUBB (A) (A) - (CY) - (Rn)
Rev. C - May 7, 1999
5.161
TSC80251
SWAP A Function:
Swap nibbles within the accumulator
Description:
Interchanges the low and high nibbles (4-bit fields) of the accumulator (bits 3-0 and bits 7- 4). This operation can also be thought of as a 4-bit rotate instruction. FLAGS : CY _ AC _ OV _ N _ Z _
Example :
The accumulator contains 0C5h (11000101B). After executing the instruction SWAP A the accumulator contains 5Ch (01011100B).
[Encoding]
1100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 Operation: SWAP (A).3:0 (A).7:4
5.162
Rev. C - May 7, 1999
TSC80251
TRAP Function:
Causes interrupt call
Description:
Causes an interrupt call that is vectored through location FF:007Bh. The operation of this instruction is not affected by the state of the interrupt enable flag in PSW0 and PSW1. Interrupt calls can not occur immediately following this instruction. FLAGS : CY _ AC _ OV _ N _ Z _
Example :
The instruction TRAP causes an interrupt call to location 0FF007Bh during normal operation.
[Encoding]
1011 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1001 Operation: TRAP SP SP - 2 (SP) PC PC (0FF007Bh)
Rev. C - May 7, 1999
5.163
TSC80251
XCh A, Function:
Exchange accumulator with byte variable
Description:
Loads the accumulator with the contents of the specified variable, at the same time writing the original accumulator contents to the specified variable. The source/destination operand can use register, direct or register-indirect addressing. FLAGS : CY _ AC _ OV _ N _ Z _
Example :
R0 contains the address 20h, the accumulator contains 3Fh (00111111B) and on-chip RAM location 20h contains 75h (01110101B). After executing the instruction XCh A,@R0. RAM location 20h contains 3Fh (00111111B) and the accumulator contains 75h (01110101B).
XCh A,dir8
[Encoding]
1100 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0101 addr7-addr0 Operation: XCh (A) (dir8)
XCh A,@Ri
[Encoding]
1100 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: XCh (A) ((Ri))
5.164
Rev. C - May 7, 1999
TSC80251
XCh A,Rn
Binary Mode Bytes States 1 3 Source Mode 2 4
[Encoding]
1100 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr Operation: XCh (A) (Rn)
Rev. C - May 7, 1999
5.165
TSC80251
XCHD A,@Ri Function:
Exchange digit
Description:
Exchanges the low nibble of the accumulator (bits 3-0) generally representing a Hexadecimal or BCD digit, with that of the on-chip RAM location indirectly addressed by the specified register. Does not affect the high nibble (bits 7-4) of either register. FLAGS : CY _ AC _ OV _ N _ Z _
Example :
R0 contains the address 20h, the accumulator contains 36h (00110110B), and on-chip RAM location 20h contains 75h (01110101B). After executing the instruction, XCHD A,@R0 on-chip RAM location 20h contains 76h (01110110B) and 35h (00110101B) in the accumulator.
[Encoding]
1101 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: XCHD (A).3:0 ((Ri)).3:0
5.166
Rev. C - May 7, 1999
TSC80251
XRL , Function:
Logical Exclusive-OR for byte variables
Description:
Performs the bitwise logical Exclusive-OR operation () between the specified variables, storing the results in the destination. The destination operand can be the accumulator, a register or a direct address. The two operands allow 12 addressing mode combinations. When the destination is the accumulator or a register, the source addressing can be register, direct, register-indirect or immediate; when the destination is a direct address, the source can be the accumulator or immediate data. Note :
When this instruction is used to modify an output Port, the value used as the original Port data is read from the output data latch, not the input pins.
FLAGS : CY _ AC _ OV _ N n Z n
Example :
The contains 0C3h (11000011B) and R0 contains 0AAh (10101010B). After executing the instruction, XRL A,R0 the accumulator contains 69h (01101001B). When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the accumulator at run time. The instruction XRL P1,#00110001B complements bits 5, 4, and 0 of output Port 1.
XRL dir8,A
[Encoding]
0110 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0010 addr7-addr0 Operation: XRL (dir8) (dir8) (A)
XRL dir8,#data
[Encoding]
0110 Rev. C - May 7, 1999 0011 addr7-addr0 immed data 5.167
TSC80251
Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: XRL (dir8) (dir8) #data
5.168
Rev. C - May 7, 1999
TSC80251
XRL A,#data
[Encoding]
0110 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0100 immed data Operation: XRL (A) (A) #data
XRL A,dir8
[Encoding]
0110 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] 0101 addr7-addr0 Operation: XRL (A) (A) (dir8)
XRL A,@Ri
[Encoding]
0110 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 011i Operation: XRL (A) (A) ((Ri))
XRL A,Rn
[Encoding]
0110 Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] 1rrr Operation: XRL (A) (A) (Rn)
XRL Rmd,Rms
[Encoding]
0110 Rev. C - May 7, 1999 1100 ssss SSSS 5.169
TSC80251
Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: XRL (Rmd) (Rmd) (Rms)
XRL WRjd,WRjs
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1101 tttt TTTT Operation: XRL (WRds) (WRjd) (WRjs)
XRL Rm,#data
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0000 Operation: XRL (Rm) (Rm) #data immed data
XRL WRj,#data16
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0100 Operation: XRL (WRj) (WRj) #data16 immed data hi immed data low
XRL Rm,dir8
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0001 Operation: XRL (Rm) (Rm) (dir8) addr7-addr0
XRL WRj,dir8
[Encoding]
5.170 Rev. C - May 7, 1999
TSC80251
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0101 Operation: XRL (WRj) (WRj) (dir8) addr7-addr0
XRL Rm,dir16
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 ssss 0011 Operation: XRL (Rm) (Rm) (dir16) addr15-addr8 addr7-addr0
XRL WRj,dir16
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 0111 Operation: XRL (WRj) (WRj) (dir16) addr15-addr8 addr7-addr0
XRL Rm,@Wrj
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] 1110 tttt 1001 Operation: XRL (Rm) (Rm) ((WRj)) ssss 0000
XRL Rm,@Drk
[Encoding]
0110 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Rev. C - May 7, 1999 1110 uuuu 1011 Operation: XRL (Rm) (Rm) ((DRk)) 5.171 ssss 0000
TSC80251
Glossary
This glossary defines acronyms, abbreviations, and terms that have special meaning in this manual.
#0data16
A 32-bit constant that is immediately addressed in an instruction. The upper 16-bit part is filled with zeros. A 32-bit constant that is immediately addressed in an instruction. The upper 16-bit part is filled with ones. 8-bit constant that is immediately addressed in an instruction. A 16-bit constant that is immediately addressed in an instruction. A constant, equal to 1, 2 or 4, that is immediately addressed in an instruction. A register or storage location that forms the result of an arithmetic or logical operation. An 11-bit destination address. The destination can be anywhere within the same 2-Kbyte block of memory as the first byte of the next instruction. A 16-bit destination address. The destination can be anywhere within the same 64-Kbyte region as the first byte of the next instruction. A 24-bit destination address. The destination can be anywhere within the 16-Mbyte address space. Arithmetic-logic unit. The part of the CPU that processes arithmetic and logical operations. The term assert refers to the act of making a signal active (enabled). The polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To assert RD# is to drive it low; to assert ALE is to drive it high. The ability of a TSC80251 microcontroller to execute, without modification, binary code written for an 80C51 microcontroller. An operating mode, selected by a configuration bit, that enables a TSC80251 microcontroller to execute, without modification, binary code written for a 80C51 microcontroller. A binary digit. An addressable bit in the C251 Architecture. An addressable bit in the C251 Architecture. Any 8-bit unit of data. glossary.1
#1data16
#data An #data16 #short accumulator
addr11
addr16
addr24
ALU
assert
binary-code compatibility
binary mode
bit bit (operand) bit51 byte Rev. C - May 7, 1999
TSC80251
clear The term clear refers to the value of a bit or the act of giving it a value. If a bit is clear, its value is "0"; clearing a bit gives it a "0" value. See program memory. Bytes that determine a set of operating parameters for the TSC80251 Product. For TSC80251 EPROM and OTPROM versions, these bytes are programmable in an EPROM area. For TSC83251 masked ROM versions, these bytes are additional information provided in a masked ROM area. For TSC80251 ROMless version, these bytes are configured in factory according to the part number. An 8-bit direct address. This can be a memory address or an SFR address. A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing. The 16-bit data pointer. In TSC80251 microcontrollers, DPTR is the lower 16 bits of the 24-bit extended data pointer, DPX. The 24-bit extended data pointer in TSC80251 microcontrollers. See also DPTR. The term deassert refers to the act of making a signal inactive (disabled). The polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To deassert RD# is to drive it high; to deassert ALE is to drive it low. A 32-bit unit of data. In memory, a double word comprises four contiguous bytes. See double word. Erasable programmable read-only memory. A 16-bit or 17-bit address presented on the device pins. The address decoded by an external device depends on how many of these address bits the external system uses. See also internal address. Any member of the set consisting of the positive and negative whole numbers and zero. The 24-bit address that the device generates. See also external address. The module responsible for handling interrupts that are to be serviced by user-written interrupt service routines. The delay between an interrupt request and the time when the first instruction in the interrupt service routine begins execution. The time delay between an interrupt request and the resulting break in the current instruction stream. The software routine that services an interrupt. Least-significant bit of a byte or a least-significant byte of a word. Most-significant bit of a byte or a most-significant byte of a word. Rev. C - May 7, 1999 code memory configuration bytes
dir8 dir16 DPTR
DPX deassert
double word dword EPROM external address
integer
internal address interrupt handler
interrupt latency
interrupt response time
interrupt service routine LSB MSB glossary.2
TSC80251
multiplexed bus OTPROM PC program memory RAM rel A bus on which the data is time-multiplexed with (some of) the address bits. One-time-programmable read-only memory, a version of EPROM. Program counter. A part of memory where instructions can be stored for fetching and execution. Random access memory A signed (two's complement) 8-bit, relative destination address. The destination is -128 to +127 bytes relative to the first byte of the next instruction. Register bits that are not used in this device but may be used in future implementations. Avoid any software dependence on these bits. In most cases: the value read from this bit is indeterminate; do not set this bit. Read only memory The term set refers to the value of a bit or the act of giving it a value. If a bit is set, its value is "1"; setting a bit gives it a "1" value. Special Function Register. A method for converting data to a larger format by filling the extra bit positions with the value of the sign. This conversion preserves the positive or negative value of signed integers. The ability of an TSC80251 microcontroller to execute recompiled source code written for an 80C51 microcontroller. An operating mode that is selected by a configuration bit. In source mode, a TSC80251 microcontroller can execute recompiled source code written for a 80C51 microcontroller. In source mode, the TSC80251 microcontroller cannot execute unmodified binary code written for an 80C51 microcontroller. See binary mode. Stack pointer. Extended stack pointer. The basic time unit of the microcontroller; the combined period of the two internal timing signals, PH1 and PH2. (The internal clock generator produces PH1 and PH2 by halving the frequency of the signal on XTAL1.) With a 16-MHz crystal, one state time equals 125 ns. Because the device can operate at many frequencies, this manual defines time requirements in terms of state times rather than in specific units of time. A 16-bit unit of data. In memory, a word comprises two contiguous bytes.
reserved bits
ROM set
SFR sign extension
source-code compatibility
source mode
SP SPX state time (or state)
word
Rev. C - May 7, 1999
glossary.3

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